Specifications

Memory Subsystem 4-7
Table 4-2 State Transition Due to Processor Activity
Processor
Request Tag Probe Result
1
Action on TLSB
TLSB
Response
Next Cache
State
Read
Read
Write
2
Write
2
Read
Read
Write
2
Write
2
Read
Read
Write
2
Write
2
Read
Write
Write
Write
Invalid
Invalid
Invalid
Invalid
_____ _____
Match AND Dirty
_____ _____
Match AND Dirty
_____ _____
Match AND Dirty
_____ _____
Match AND Dirty
_____
Match AND Dirty
_____
Match AND Dirty
_____
Match AND Dirty
_____
Match AND Dirty
Match
______
Match AND Shared
Match AND Shared
Match AND Shared
Read
Read
Read
Read
Read
Read
Read
Read
Read, Victim
Read, Victim
Read, Victim
Read, Victim
None
None
Write
Write
______
Shared
Shared
______
Shared
Shared
______
Shared
Shared
______
Shared
Shared
______
Shared
Shared
______
Shared
Shared
None
None
______
Shared
Shared
3
______ _____
Shared, Dirty
_____
Shared, Dirty
______
Shared, Dirty
_____
Shared, Dirty
______ _____
Shared, Dirty
_____
Shared, Dirty
______
Shared, Dirty
_____
Shared, Dirty
______ _____
Shared, Dirty
_____
Shared, Dirty
______
Shared, Dirty
_____
Shared, Dirty
No change
______
Shared, Dirty
______ _____
Shared, Dirty
_____
Shared, Dirty
______
1
An overscore on a cache block status bit indicates the complement of the state. For example, Shared = Not Shared.
2
The cache is read-allocate. Writes that miss in the cache are issued as read miss modifies or read miss STxC to the
system.
3
The DECchip 21164 presumes that writes invalidate the block in all caches in the system. For Memory Channel
writes, the CPU module forces the block back to the shared state. The cache remaining in the shared state is a func-
tion of the fact that this was a Memory Channel operation (that is, the address fell in the space defined for Memory
Channel), NOT due to the shared response on the bus. A shared response on the bus to a write to memory space not
within Memory Channel will not keep the block in the shared state.