Specifications

x
DDR0:3—Data Diagnostic Registers ................................................................ 7-106
7.6 I/O Port-Specific Registers........................................................................................ 7-109
RMRR0-1—Memory Channel Range Registers ................................................ 7-110
ICCMSR—I/O Control Chip Mode Select Register........................................... 7-112
ICCNSE—I/O Control Chip Node-Specific Error Reg ...................................... 7-117
ICCDR—I/O Control Chip Diagnostic Register ................................................ 7-122
ICCMTR—I/O Control Chip Mailbox Transaction Reg .................................... 7-125
ICCWTR—I/O Control Chip Window Transaction Reg.................................... 7-127
IDPNSE0–3—I/O Data Path Node-Specific Error Regs .................................. 7-128
IDPDRn—I/O Data Path Diagnostic Registers................................................. 7-133
IDPVR—I/O Data Path Vector Register .......................................................... 7-137
IDPMSR—I/O Data Path Mode Select Register ............................................... 7-138
IBR—Information Base Repair Register........................................................... 7-140
7.7 KFTIA Specific Registers.......................................................................................... 7-142
Chapter 8 Interrupts
8.1 Vectored Interrupts....................................................................................................... 8-1
8.1.1 I/O Port Interrupt Rules......................................................................................... 8-1
8.1.2 CPU Interrupt Rules .............................................................................................. 8-2
8.1.3 I/O Port Interrupt Operation ................................................................................. 8-2
8.2 Nonvectored Interrupts ................................................................................................ 8-3
8.3 I/O Interrupt Mechanism ............................................................................................. 8-3
8.3.1 TLSB Principles for Interrupts.............................................................................. 8-3
8.3.1.1 Virtual Node Identification - TLVID............................................................... 8-4
8.3.1.2 Directing Interrupts - TLCPUMASK.............................................................. 8-4
8.3.1.3 Directing Interrupts - TLINTRMASK ............................................................ 8-4
8.3.1.4 Interrupt Registers - TLIOINTR4–8............................................................... 8-4
8.3.2 Generating Interrupts............................................................................................ 8-5
8.3.3 Servicing Interrupts ............................................................................................... 8-5
8.3.4 Interprocessor Interrupts....................................................................................... 8-5
8.3.5 Module-Level Interrupts ........................................................................................8-6
Glossary
Figures
1-1 AlphaServer 8400 System Block Diagram..............................................................1-2
2-1 TLSB Memory Address Bit Mapping ...................................................................... 2-7
2-2 Address Decode....................................................................................................... 2-10
2-3 64-Bit ECC Coding Scheme ................................................................................... 2-21
2-4 TLSB CSR Address Bit Mapping ..........................................................................2-26
2-5 TLSB CSR Space Map............................................................................................ 2-27
2-6 Mailbox Data Structure .........................................................................................2-30
2-7 TLRDRD Register .................................................................................................. 2-33
3-1 CPU Module Simple Block Diagram .......................................................................3-2
3-2 Physical Address Space Map ................................................................................... 3-6
3-3 TLSB CSR Space Map.............................................................................................. 3-8
3-4 Gbus Map.................................................................................................................. 3-9
3-5 PCI Programmer’s Address....................................................................................3-11
4-1 Cache Index and Tag Mapping to Block Address (4MB)........................................ 4-3
4-2 Cache Index and Tag Mapping to Block Address (1MB)........................................ 4-3