AlphaServer 8200/8400 System Technical Manual Order Number EK–T8030–TM. A01 The Digital AlphaServer 8200 and 8400 systems are designed around the DECchip 21164 CPU. The TLSB is the system bus that supports nine nodes in the 8400 system and five nodes in the 8200 system. The AlphaServer 8400 can be configured with up to six single or dual processor CPU modules (KN7CC), seven memory modules (MS7CC), and three I/O modules (KFTHA and KFTIA).
First Printing, May 1995 The information in this document is subject to change without notice and should not be construed as a commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for any errors that may appear in this document. The software, if any, described in this document is furnished under a license and may be used or copied only in accordance with the terms of such license.
Contents Preface ............................................................................................................................................ xv Chapter 1 1.1 1.2 1.3 1.3.1 1.3.2 1.3.3 1.3.4 1.4 1.5 1.6 1.6.1 1.6.2 1.6.3 1.6.4 1.6.4.1 1.6.4.2 1.6.4.3 Configuration ................................................................................................................ 1-1 Bus Architecture ..............................................................................................
2.2.4.3 Address Bus Transactions ............................................................................. 2-12 2.2.4.4 Module Transactions ...................................................................................... 2-12 2.2.4.5 Address Bus Priority ...................................................................................... 2-12 2.2.4.6 Address Bus Request ..................................................................................... 2-13 2.2.4.7 Asserting Request ..........
2.4.3.8 2.4.3.9 2.4.4 2.4.4.1 2.4.4.2 2.4.4.3 2.4.4.4 2.4.4.5 2.4.4.6 2.4.4.7 2.4.4.8 2.4.5 2.4.6 2.4.6.1 2.4.6.2 Multiple Address Bus Errors ......................................................................... 2-38 Summary of Address Bus Errors .................................................................. 2-38 Data Bus Errors .................................................................................................... 2-39 Single-Bit ECC Errors ............................................
Chapter 4 4.1 4.1.1 4.1.2 4.1.3 4.2 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.7 4.2.8 4.2.9 4.2.10 4.3 4.3.1 4.3.1.1 4.3.1.2 4.3.1.3 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.6.1 4.3.6.2 4.3.6.3 4.3.6.4 Internal Cache ............................................................................................................... 4-1 Instruction Cache ................................................................................................... 4-1 Data Cache ......................................................
5.2.2.3 5.2.2.4 5.2.2.5 5.2.3 5.2.3.1 5.2.3.2 5.2.3.3 5.2.4 5.3 5.3.1 5.3.1.1 5.3.1.2 5.3.1.3 5.3.1.4 5.3.2 5.3.2.1 5.3.2.2 5.3.2.3 5.3.2.4 CSR Write Data ECC Check ......................................................................... 5-10 Forcing Write Errors for Diagnostics ............................................................ 2-15 Write Data Out Selection .............................................................................. 2-15 Read Data Output Logic ................................
6.5.3 Error Detection Schemes ..................................................................................... 6-34 6.6 Hose Interface ............................................................................................................. 6-35 6.6.1 Hose Protocol ....................................................................................................... 6-35 6.6.2 Window Space Mapping ....................................................................................... 6-36 6.6.2.
Chapter 7 7.1 7.2 7.3 7.4 7.5 System Registers Register Conventions .................................................................................................... 7-1 Register Address Mapping ........................................................................................... 7-2 TLSB Registers ............................................................................................................. 7-4 TLDEV—Device Register ...............................................................
7.6 7.7 DDR0:3—Data Diagnostic Registers ................................................................ 7-106 I/O Port-Specific Registers ........................................................................................ 7-109 RMRR0-1—Memory Channel Range Registers ................................................ 7-110 ICCMSR—I/O Control Chip Mode Select Register ........................................... 7-112 ICCNSE—I/O Control Chip Node-Specific Error Reg ......................................
4-3 4-4 4-5 4-6 4-7 5-1 5-2 5-3 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 6-17 6-18 6-19 6-20 6-21 6-22 6-23 6-24 6-25 6-26 6-27 6-28 6-29 6-30 6-31 6-32 6-33 6-34 6-35 7-1 Cache Index and Tag Mapping to Block Address (16MB) ...................................... 4-4 Memory Module Block Diagram ............................................................................ 4-10 Two-Way Interleave of a 128-Mbyte DRAM Array ..............................................
2-7 2-8 2-9 2-10 2-11 2-12 3-1 3-2 3-3 3-4 3-5 3-6 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 5-1 5-2 5-3 5-4 5-5 5-6 5-7 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 6-17 6-18 6-19 6-20 6-21 6-22 6-23 6-24 6-25 6-26 6-27 6-28 6-29 xii TLSB Node Base Addresses ....................................................................................... 2-28 TLSB CSR Address Mapping ..................................................................................... 2-29 Mailbox Data Structure ..
6-30 6-31 6-32 6-33 6-34 6-35 6-36 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 7-19 7-20 7-21 7-22 7-23 7-24 7-25 7-26 7-27 7-28 7-29 7-30 7-31 7-32 7-33 7-34 7-35 7-36 7-37 7-38 7-39 7-40 7-41 7-42 7-43 7-44 7-45 7-46 7-47 7-48 7-49 DMA Masked Write Packet Sizes .............................................................................. 6-58 DMA Unmasked Write Packet Description ...............................................................
7-50 7-51 7-52 7-53 7-54 7-55 7-56 7-57 7-58 7-59 7-60 7-61 7-62 7-63 7-64 7-65 8-1 xiv STDER A, B, C, D Register Bit Definitions ............................................................. 7-104 STDERE Register Bit Definitions ............................................................................ 7-105 DDRn Register Bit Definitions ................................................................................. 7-106 I/O Port-Specifc Registers ....................................................
Preface Intended Audience This manual is intended for developers of system software and for service personnel. It discusses the AlphaServer 8200/8400 systems that are designed around the DECchip 21164 CPU and use the TLSB bus as the main communication path between all the system modules. The manual describes the operations of all components of the system: the TLSB bus, CPU modules, memory modules, and the I/O modules. It discusses in detail the functions of all registers in the system.
KFTIA and KFTHA support the PCI bus, XMI bus, and the Futurebus+, depending on the system in which they are used. The chapter describes the transaction types on the TLSB interface and the hose interface. It presents a brief survey of the integrated I/O port (KFTIA). The survey focuses mainly on the integrated I/O section of the module, which provides two PCI buses that support ports for PCI devices such as Ethernet, SCSI, FDDI, and NVRAM.
Table 1 Digital AlphaServer 8200/8400 Documentation Title Order Number Hardware User Information and Installation Operations Manual EK–T8030–OP Site Preparation Guide EK–T8030–SP AlphaServer 8200 Installation Guide EK–T8230–IN AlphaServer 8400 Installation Guide EK–T8430–IN Service Information Kit QZ–00RAC–GC Service Manual (hard copy) EK–T8030–SV Service Manual (diskette) AK–QKNFA–CA Reference Manuals System Technical Manual EK–T8030–TM DWLPA PCI Adapter Technical Manual EK–DWLPA–TM Upg
Table 1 Digital AlphaServer 8200/8400 Documentation (Continued) Title Order Number KZMSA Adapter Installation Guide EK–KXMSX–IN RRDCD Installation Guide EK–RRDRX–IN Upgrade Manuals: 8200 System Only DWLPA PCI Shelf Installation Guide EK–DWL82–IN H7266 Power Regulator Installation Card EK–H7266–IN H7267 Battery Backup Installation Card EK–H7267–IN xviii
Table 2 Related Documents Title Order Number General Site Preparation Site Environmental Preparation Guide EK–CSEPG–MA System I/O Options BA350 Modular Storage Shelf Subsystem Configuration Guide EK–BA350–CG BA350 Modular Storage Shelf Subsystem User’s Guide EK–BA350–UG BA350-LA Modular Storage Shelf User’s Guide EK–350LA–UG CIXCD Interface User Guide EK–CIXCD–UG DEC FDDIcontroller 400 Installation/Problem Solving EK–DEMFA–IP DEC FDDIcontroller/Futurebus+ Installation Guide EK–DEFAA–IN DEC F
Chapter 1 Overview The computer system is an AlphaGeneration server very similar to but with twice the performance of DEC 7000/10000 systems. It is built around the TLSB bus and supports the OpenVMS Alpha and Digital UNIX operating systems. It is manufactured in two models: AlphaServer 8200 and AlphaServer 8400. The AlphaServer 8400 features nine nodes, while AlphaServer 8200 supports only five nodes.
Futurebus+, or PCI bus. The local I/O options on the integrated I/O port appear to software as a PCI bus connected to a hose. Figure 1-1 shows a block diagram of the 8400 system.
bus transactions may be overlapped, and these transactions may be overlapped with bus arbitration. Arbitration priority rotates in a round-robin scheme among the nodes. A node in the slot dedicated to I/O follows a special arbitration algorithm so that it cannot consume more than a certain fraction of the bus bandwidth. The TLSB supports a conditional write-update cache protocol.
to the DECchip 21164 Functional Specification for a complete description of the DECchip 21164 and PALcode. 1.3.2 Backup Cache Each backup cache (B-cache) is four Mbytes in size. In a dual-processor module there are two independent backup caches, one for each CPU. Each B-cache is physically addressed, direct-mapped with a 64-byte block and fill size. The B-cache is under the direct control of the DECchip 21164.
ported by a single motherboard design. The 2-Gbyte memory option uses a different motherboard and SIMM design. A maximum of seven memory modules may be configured on the TLSB (in a system with one CPU module and one I/O module). Thus, the maximum memory size is 14 Gbytes, using 2-Gbyte modules. Memory operates within the 10–30 ns TLSB cycle time range. To keep memory latency low, the memory module supports three different DRAM cycle times.
tion to two 10BaseT Ethernet ports, one FDDI port, and three FWD and one single-ended SCSI ports. The DWLMA is the interface between a hose and a 14-slot XMI bus. It manages data transfer between XMI adapters and the I/O port. The DWLAA is the interface between a hose and a 10-slot Futurebus+ card cage. It manages data transfer between Futurebus+ adapters and the I/O port. The DWLPA is the interface between a hose and a 12-slot, 32-bit PCI bus. It manages data transfer between PCI adapters and the I/O port.
• KDM70 – XMI to SI disk/tape • KZMSA – XMI to SCSI disk/tape • KFMSB – XMI to DSSI disk/tape and OpenVMS clusters • CIXCD-AC – XMI to CI HSC disk/tape and OpenVMS clusters • DEMNA – XMI to Ethernet networks and OpenVMS clusters • DEMFA – XMI to FDDI networks and OpenVMS clusters • DEFAA – Futurebus+ to FDDI networks and OpenVMS clusters Booting is suported from PCI SCSI disk, Ethernet, and FDDI devices. 1.6.2 OpenVMS Alpha OpenVMS Alpha fully supports the system.
— Cache/memory exerciser — I/O port/DWLMA loopback exerciser — Disk/tape device exerciser — Network exerciser — FBE exerciser — XCT (XMI bus exerciser) exerciser • Manual tests A subset of these diagnostics is invoked at system power-up. Optionally, they may be invoked on every system boot. The subset can also be invoked by the user through console command. Note that any of the diagnostics listed above can be individually invoked by the user through console command. 1.6.4.
Chapter 2 TLSB Bus This chapter provides a brief overview of the TLSB bus. For more detailed discussions and timing diagrams for the various bus cycles, refer to the TurboLaser System Bus Specification. 2.1 Overview The TLSB bus is a limited length, nonpended, synchronous bus with a separate address and data path. Ownership of the address bus is determined using a distributed arbitration protocol. The data bus does not require an arbitration scheme.
2.1.1 Transactions A transaction couples a commander node that issues the request and a slave node that sequences the data bus to transfer data. This rule applies to all transactions except CSR broadcast space writes. In these transactions, the commander is responsible for sequencing the data bus. CPUs and I/O nodes are always the commander on memory transactions and can be either the commander or the slave on CSR transactions. Memory nodes are slaves in all transactions.
The TLSB implements parity checking on all address and command fields on the address bus, ECC protection on the data field, and protocol sequence checking on the control signals across both buses. 2.1.5 TLSB Signal List Table 2-1 lists the signals on the TLSB. Signal name, function, and default state are given. After initialization, the bus drives the default value when idle.
Table 2-1 TLSB Bus Signals (Continued) Signal Name TLSB_PS_TX L TLSB_EXP_SEL<1:0> L TLSB_SECURE L LDC_PWR_OK L PIU_A_OK L PIU_B_OK L TLSB_RUN L TLSB_CON_WIN L ON_CMD SEQ_DCOK TLSB_DCOK L EXT_VM_ENB VM3 VM5 V3_OUT V5_OUT GB2CCLSPA MFG_MODE L SER_NUM_CLK SER_NUM_DAT 2-4 TLSB Bus Default State H H L L L L H H L Function Power supply transmit status Expander select Secure console Local disk converter I/O unit A power OK I/O unit B power OK System run indicator Console win status DC-DC converter power on ena
2.2 Operation This section offers an overview of the TLSB bus operations. Topics include: • Physical node identification • Virtual node identification • Address bus concepts • Address bus arbitration • Address bus cycles • Address bus commands • Data bus concepts • Data bus functions • Miscellaneous bus signals The reader is referred to the engineering specification for more detail on the topics covered in this chapter. 2.2.
2.2.2 Virtual Node Identification TLSB system operation requires that certain functional units can be identified uniquely, independent of their physical location. Specifically, individual memory banks and CPUs must be uniquely addressable entities at the system level. As multiple memory banks and CPUs are implemented on single modules, a physical node ID is insufficient to uniquely address each bank or each CPU.
drive the address and command, the outcome of the tag lookup can be evaluated by the bus interface. If the lookup is a hit, then the CPU bus interface nulls the TLSB command field and cancels the request. Although this consumes potentially needed address bus slots, the address bus requires two cycles to initiate a command and the data bus requires three cycles per transaction. This means that there are surplus address bus slots beyond the number required to keep the data bus busy.
2.2.3.1 Memory Bank Addressing Scheme The TLSB supports one terabyte of physical memory. The memory address space is accessed by a 40-bit byte address. The granularity of accesses on the TLSB is a 64-byte cache block. I/O adapters that need to manipulate data on boundaries less than 64 bytes require the commander node to perform an atomic Read-Modify-Write transaction. Physical memory on the TLSB is broken into banks. The commander decodes the 40-bit physical address into a memory bank number.
2.2.3.3 Memory Bank Address Decoding The minimum bank size for the TLSB address decode scheme is 64 Mbytes. To address memory, a CPU or I/O node must perform a memory bank decode to test the status of the bank. The memory modules transmit the status of each bank on the 16 TLSB_BANK_AVL lines. This permits a node to sense the state of the bank from the bus. The TLSB early arbitration scheme allows a node to request the bus before the bank decode takes place.
Figure 2-2 Address Decode 39 26 25 Physical Address ADRMASK 12 ADDRESS Decode and Mask Decode and Mask Compare 8 6 PHAdr 0 10 1 8 Address Hit INTMASK INTLV Mask Mask Compare Interleave Hit Valid AND Bank Hit BXB0830.AI When a physical address is presented to the bank decode logic, all valid address bits, as determined by the ADRMASK field, are compared with their corresponding physical address bits.
2.2.3.4 Bank Available Status TLSB_BANK_AVL indicates that a bank is available for use. When not asserted, no requests except Write Bank Unlock can be issued to that bank. Each memory bank has one of the TLSB_BANK_AVL<15:0> signals assigned to it by the console. The number of the TLSB_BANK_AVL bit corresponds to the bank number assigned to that bank.
2.2.4 Address Bus Arbitration The TLSB bus has demultiplexed address and data buses. These buses operate independently and are related only in as much as a valid command on the address bus will result in a data transfer on the data bus at some later time. 2.2.4.1 Initiating Transactions To initiate a bus transaction, a module must request the bus and arbitrate for access to the bus with other requesting modules.
Consequently, the priority of any device will eventually bubble up to the highest level. The no-op command is the only non-data transfer command; it does not affect priorities. TLSB_REQ8_HIGH and TLSB_REQ8_LOW are assigned to the I/O module in node 8. These lines represent the highest and the lowest arbitration priorities. The I/O port uses the high-priority line to guarantee a worstcase latency.
in a request cycle, that CPU must take part in the following arbitration cycle even if the bus is no longer required. If the device wins the bus, it asserts a no-op on the bus command lines. I/O devices in the dedicated I/O port node cannot use early arbitration. 2.2.4.9 False Arbitration Effect on Priority Relative bus priorities are only updated when a data transfer command is asserted on the bus. If a device false arbitrates and drives a no-op on the bus, the bus priorities are not updated. 2.2.4.
CPUs can request the bus without first checking that the bank is busy. If the bank does turn out to be busy, this is considered a false arbitration, and the command is a no-op. The device can request the bus again when the bank is free. To prevent lockout of devices that might have been waiting for the bank, CPUs early arbitrating for the bus cannot issue the command if they request in the cycle when asserts on the bus, or in the subsequent cycle.
in subsequent CSR accesses, and it is not ready to source or accept data, it can delay asserting TLSB_SEND_DATA, or it can assert TLSB_HOLD on the bus. 2.2.4.15 Command Acknowledge When a device asserts an address, bank number, and a valid data transfer command on the bus, the targeted device responds two cycles later by asserting TLSB_CMD_ACK. This indicates that the command has been received and that the targeted address is valid.
• No-op command cycles Two signals are used to provide parity protection on the address bus during all command cycles. TLSB_CMD_PAR is asserted to generate odd parity for the signals TLSB_CMD<2:0>, TLSB_BANK_NUM<3:0>, TLSB_ADR<39:31>, and TLSB_ADR<4:3>. TLSB_ADR_PAR is asserted to generate odd parity for the signals TLSB_ADR<30:5>. When not in use, idle address bus cycles have a predictable value, called the default bus value. The default value is given in Table 2-1. 2.2.
Write Bank Unlock Used by the I/O port to complete a Read-Modify-Write. Writes the data specified by the address and bank number and unlocks the bank. CSR Read Read the CSR location specified by the address. Bank number specifies a CPU virtual ID. CSR Write Write the CSR location specified by the address. Bank number specifies a CPU virtual ID. 2.2.7 Data Bus Concepts The TLSB transfers data in the sequence order that valid address bus commands are issued.
2.2.7.3 Back-to-Back Return Data Two memory read transactions are returned back to back as follows. TLSB_SEND_DATA for the first transaction is asserted, and the shared and dirty state is driven to the bus. Three cycles after the first TLSB_SEND_DATA assertion, the second memory initiates its transfer. The two transfers proceed normally, piped three cycles apart. 2.2.7.4 Back-to-Back Return with HOLD TLSB_HOLD is asserted in response to the first TLSB_SEND_DATA.
If one CPU drives TLSB_HOLD while another drives TLSB_SHARED or TLSB_DIRTY, the second keeps driving TLSB_SHARED and TLSB_DIRTY. TLSB_HOLD, TLSB_SHARED, and TLSB_DIRTY are asserted for one cycle and deasserted in the next cycle. This two-cycle sequence repeats until TLSB_HOLD is not reasserted (the no-Hold cycle). Receivers internally convert TLSB_HOLD to appear asserted in both cycles. The value received from the bus in the second cycle is Unpredictable.
Table 2-5 2.2.8.6 TLSB Data Wrapping TLSB_ADR<5> Data Cycle Data Bytes 0 0 0–31 0 1 32–63 1 0 32–63 1 1 0–31 ECC Coding Data is protected using quadword ECC. The 256-bit data bus is divided into four quadwords.
Check bits are computed by XORing all data bits corresponding to columns containing a one in the upper table and inverting bits <3:2>. These check bits are transmitted on the TLSB_ECC lines. An error syndrome is computed by XORing all data and check bits corresponding to columns containing a one in both tables and inverting bits <3:2>. A syndrome equal to zero means no error. A syndrome equal to one of the hex syndromes in the tables indicates the data or check bit in error.
TLSB_SHARED is valid when driven in response to Read, Read Bank Lock, Write, and Write Bank Unlock commands. Nodes may, therefore, drive TLSB_SHARED in response to any command; the value of TLSB_SHARED is only guaranteed to be accurate when TLSB_SHARED is asserted in response to the commands named above. 2.2.8.10 TLSB_DIRTY The TLSB_DIRTY signal is used to indicate that the block being accessed is valid in a CPU’s cache, and that the copy there is more recent than the copy in memory.
2.2.9 Miscellaneous Bus Signals Several signals are required for correct system operation. They are: • TLSB_DATA_ERROR — A hard or soft data error has occurred on the data bus. • TLSB_FAULT — A system fatal event has occurred. • TLSB_RESET — Reset the system and initialize. • TLSB_LOCKOUT — Lockout request to break deadlock. TLSB_DATA_ERROR The TLSB_DATA_ERROR signal is used to broadcast the detection of hard and soft data errors on the data bus to other nodes.
and allows the CPUs asserting TLSB_LOCKOUT to complete their bus access without interference. TLSB_LOCKOUT is asserted for one cycle then deasserted for one cycle. This two-cycle sequence may be repeated until the device is ready to deassert TLSB_LOCKOUT. Multiple devices may assert this signal in any of these two-cycle sequences. Devices must disregard the value of TLSB_LOCKOUT received during the second of each two-cycle sequence, as it is Unpredictable.
Figure 2-4 TLSB CSR Address Bit Mapping 39 3 2 0 Processor Byte Address 39 3 CSR Address Address Bus Field BXB0827.AI 2.3.1 CSR Address Space Regions A total of 1 terabyte of physical address space can be mapped directly to the TLSB. Physical address bit <39> normally indicates an I/O space reference from the CPU, so the first 512 Gbytes are reserved, and all address bits can be mapped directly to the TLSB address bus. Physical address bits <2:0> do not appear on the bus.
Figure 2-5 TLSB CSR Space Map Byte Address F0 0000 0000 FF 87FF FFC0 FF 8800 0000 FF 883F FFC0 FF 8840 0000 FF 887F FFC0 . . . Reserved Node 0 CSRs: 64K CSR Locations Node 1 CSRs: 64K CSR Locations . . . FF 8A00 0000 Node 8 CSRs: 64K CSR Locations FF 8A3F FFC0 FF 8A40 0000 FF 8DFF FFC0 FF 8E00 0000 Reserved Broadcast Space: 64K CSR Locations FF 8E3F FFC0 FF 8E40 0000 Reserved FF FFFF FFC0 BXB-0780A-94 All TLSB node CSRs are 32 bits wide, except the TLMBPR and TLRDRD registers, which are wider.
Table 2-7 TLSB Node Base Addresses Node Number BB Address <39:0> Module 0 1 2 3 4 5 6 7 8 FF 8800 0000 FF 8840 0000 FF 8880 0000 FF 88C0 0000 FF 8900 0000 FF 8940 0000 FF 8980 0000 FF 89C0 0000 FF 8A00 0000 CPU, Memory CPU, Memory CPU, Memory CPU, Memory CPU, Memory, I/O CPU, Memory, I/O CPU, Memory, I/O CPU, Memory, I/O I/O Table 2-8 shows the mapping of CSRs to node space and broadcast space locations.
Table 2-8 TLSB CSR Address Mapping Address Name Mnemonic Modules That Implement BB+000 BB+040 BB+080 BB+0C0 BB+200 BB+240 BB+280 BB+2C0 BB+300 BB+340 BB+380 BB+3C0 BB+600 BB+640 BB+680 BB+6C0 BB+700 BB+740 BB+A00 BB+A40 BB+A80 BB+AC0 BB+B00 BB+C001 BSB+000 BSB+040 BSB+100 BSB+140 BSB+180 BSB+1C0 BSB+200 BSB+400 BSB+440 BSB+480 BSB+4C0 BSB+500 BSB+600 BSB+640 BSB+800 BSB+840 BSB+1880 Device Register Bus Error Register Configuration Register Virtual ID Register Memory Mapping Register Memory Mapping Re
2.3.2 TLSB Mailboxes CSRs that exist on external I/O buses connected to an I/O port (or another I/O module implementing mailbox register access) are accessed through mailbox structures that exist in main memory. Read requests are posted in mailboxes, and data and status are returned in the mailbox. Mailboxes are allocated and managed by operating system software (successive operations must not overwrite data that is still in use).
Table 2-9 describes the mailbox data structure. Table 2-9 Mailbox Data Structure QW Bit(s) Name Description 0 <29:0> CMD Remote Bus Command. Controls the remote bus operation and can include fields such as address only, address width, and data width. See Alpha SRM. <30> B Remote Bridge Access. If set, the command is a special or diagnostic command directed to the remote side. See Alpha SRM. <31> W Write Access. If set, the remote bus operation is a write. <39:32> MASK Disable Byte Mask.
structure. Software may choose to reuse mailboxes (for example, multiple reads from the same CSR), or it may maintain templates that are copied to the mailbox. Byte masks may be needed by some hardware devices for correct operation of a CSR read as well as a CSR write. A bit is set in the mailbox MASK field to disable the corresponding byte location to be read or written. See the Alpha SRM for more details on the use of the mailbox. 2.3.
predictable as the value has no significance. The I/O node may choose not to acknowledge the command and save data bus cycles. The I/O node proceeds to read the selected remote CSR. When the data is available and there are no errors reading the data, the I/O node issues a CSR write command to a CSR Read Data Return Data (TLRDRD) Register in local CSR broadcast space.
2.4.1 Error Categories Error occurrences can be categorized into four groups: 2.4.1.1 • Hardware recovered soft errors • Software recovered soft errors • Hard errors • System fatal errors Hardware Recovered Soft Errors Soft errors of this class are recoverable and the system continues operation. When an error occurs, a soft error interrupt is generated to inform the operating system of the error. An example of this class of error is a single-bit error in a data field that is ECC protected.
2.4.2 Error Signals The TLSB provides two signals for broadcasting the detection of an error to other nodes. All nodes monitor the error signals, TLSB_DATA_ERROR and TLSB_FAULT (Section 2.2.9) , to latch status relative to the error. Except for system fatal errors, only the commander (CPU or I/O node) checks whether a command completes with or without errors. The commander monitors the error signals to determine if any error was detected by another node.
every cycle, enabled solely by the driven assertion value. For example, TLSB_CMD_ACK is assertion checked to verify that if this node attempts to assert it, the signal is received asserted. If this node is not asserting TLSB_CMD_ACK, possibly some other node is asserting it.
When a commander node issues a CSR access command but does not receive acknowledgment, it sets in the TLBER register. Only the commander that issues the command detects this error and sets . The error is not broadcast and handling is node specific. The exception to this rule is a CSR write to a Mailbox Pointer Register; no acknowledgment is not regarded as an error and handling is node specific.
BER is set if the Write Bank Unlock command appears on the bus before the second data cycle of the preceding Read Bank Lock command. If any node receives a CSR access command (to any address) while a CSR command is in progress, the node sets TLBER and asserts TLSB_FAULT six cycles after the command. A node sets TLBER if a new CSR command appears on the bus in or prior to the second data cycle of the preceding CSR command.
Table 2-10 Address Bus Error Summary Error Description Who Detects Signal ATCE Address Transmit Check Error Commander TLSB_FAULT APE Address Parity Error All TLSB_FAULT 1 BBE Bank Busy Violation Error All LKTO Bank Lock Timeout Memory None NAE No Acknowledge to CSR Access Commander None FNAE No Acknowledge to Memory Access Commander TLSB_FAULT RTCE Request Transmit Check Error Commander TLSB_FAULT ACKTCE Acknowledge Transmit Check Error Slave TLSB_FAULT MMRE Memory Mappin
2.4.4.1 Single-Bit ECC Errors A single-bit error on a memory data transfer is detected by a node’s ECC checking logic. The decision to correct the data or not is implementation specific. If a node detects a single-bit ECC error, it logs the error in the TLESRn register by setting either or , depending on whether a read or write command failed. If a memory node detects an ECC error in a memory lookup, the memory flags the error by also setting .
This timeout can be disabled by software. The bit in the TLCNR register prevents from setting. It does not clear if already set. 2.4.4.5 Data Status Errors The TLSB_STATCHK signal is used as a check on TLSB_SHARED and TLSB_DIRTY. When TLSB_SHARED and TLSB_DIRTY are expected to be valid on the bus, TLSB_STATCHK is read and compared with them.
System fatal data bus errors are cumulative. Should a second system fatal error occur, TLSB_FAULT is asserted a second time. If a fatal error is of a different type than the first, an additional error is set in the TLBER register. 2.4.4.8 Summary of Data Bus Errors Table 2-12 shows all the data bus errors, which nodes are responsible for detecting the errors, and what error signals are asserted.
Some errors are more important to software than others. For example, should two correctable data errors occur, one during a write to memory and the other during a read from memory, the error during the write would be more important. The software can do no more than log the read error as it should be corrected by hardware. But the memory location is written with a single-bit data error. Software may rewrite that memory location so every read of that location will not report an error in the future.
The CSR registers contain information about the error. The commander’s TLBER register contains either correctable or uncorrectable error status, and the TLFADRn registers contain the command code, bank number, and possibly the address. If TLSB_DATA_ERROR asserted, the node that transmitted the data will have set the . If is set in a memory node, there were only two nodes involved in the data transfer. If is set in a node with cache, this is the third node that transmitted dirty data.
2.4.6.2 Write Errors Write data operations involve a minimum of two nodes. The commander issues the command and transmits the data. A memory node acknowledges as the slave, provides the timing for the data transaction, and receives the data. All other nodes check to see if their cache is sharing the data and may assert TLSB_SHARED. Nodes that assert TLSB_SHARED may also receive the data and check it for errors, or they may invalidate the block in their cache.
still cause interrupts. Interrupts for correctable read data errors should also be disabled, as read errors will result from not correcting the singlebit errors in data that gets written into memory. Disabling correctable write data errors involves setting in the TLCNR register of all nodes in the system. The bit tells all nodes to disable asserting TLSB_DATA_ERROR on correctable write data errors.
Chapter 3 CPU Module The CPU module is a DECchip 21164 based dual-processor CPU module. Each CPU chip has a dedicated 4-Mbyte module-level cache (B-cache) and a shared interface to memory and I/O devices through the TLSB bus. 3.
Figure 3-1 CPU Module Simple Block Diagram 21164A 21164A Data Buffer DIGA DIGA CMD/Addr CMD/Addr MMG Cache Data Bus B-Cache Addr B-Cache Addr Data Bus Cache Data Buffer ADG DIGA DIGA TLSB Bus BXB0825.AI 3.1.1 DECchip 21164 Processor The DECchip 21164 microprocessor is a CMOS-5 (0.5 micron) superscalar, superpipelined implementation of the Alpha architecture.
• On-chip 8-Kbyte virtual instruction cache with seven-bit ASNs (MAX_ASN=127). • On-chip dual-read-ported 8-Kbyte data cache (implemented as two 8Kbyte data caches containing identical data). • On-chip write buffer with six 32-bit entries. • On-chip 96-Kbyte 3-way set associative writeback second-level cache. • Bus interface unit that contains logic to access an optional third-level writeback cache without CPU module action. The size and access time of the third-level cache are programmable.
To facilitate the multiplexing of the 256 bits of TLSB data to the 128 bits required by the DECchip 21164 interface, longwords (0,4), (1,5), (2,6) and (3,7) are paired together. This pairing is achieved by "criss-crossing" the signals coming from the TLSB connector to the DIGA pins. The DIGA transfers CSR data to/from the ADG and data path. It contains registers to support I/O and interprocessor interrupts, and diagnostic functions. The DIGA also provides an access path to the Gbus logic and the MMG. 3.1.
• A set of module-level parallel I/O ports for functions such as LED status indicators and node identification • Two serial I/O ports connected to the serial ROM I/O of the DECchip 21164’s for manufacturing diagnostic use • Support for serial number loading Communications to the UARTs, FEPROMs, watch chip, LED control registers, and other registers are accomplished over the 8-bit wide Gbus. 3.2.
Table 3-1 Directly Addressable Console Hardware Console Hardware Address FEPROM FEPROM Reserved Reserved UART chip Watch chip GBUS$WHAMI GBUS$LED0 GBUS$LED1 GBUS$LED2 GBUS$MISCR GBUS$MISCW GBUS$TLSBRST GBUS$SERNUM GBUS$TEST FF 9000 0000 - FF 93FF FFC0 FF 9400 0000 - FF 97FF FFC0 FF 9800 0000 - FF 9BFF FFC0 FF 9C00 0000 - FF 9FFF FFC0 FF A000 0000 - FF A100 00C0 FF B000 0000 - FF B000 0FC0 FF C000 0000 FF C100 0000 FF C200 0000 FF C300 0000 FF C400 0000 FF C500 0000 FF C600 0000 FF C700 0000 FF C800 0000
from cache or the TLSB as shown in Table 3-2. Bit <4> specifies which 16-byte portion of the 32-byte subblock is returned first from the DIGA or cache. Bits <3:0> specify the byte being accessed.
3.3.2 I/O Space The I/O space contains the I/O window space, TLSB CSR space, module Gbus space, and DECchip 21164 private CSR space. It is selected when bit <39> is one. 3.3.2.1 I/O Window Space This space, defined by addresses in the range 80 0000 0000 to DF FFFF FFC0 is used for PCI bus addressing. I/O window space support is discussed in Section 3.4. 3.3.2.2 TLSB CSR Space All TLSB CSR registers (except TLMBPRx) are 32 bits wide and aligned on 64-byte boundaries. (TLMBPR registers are 38 bits wide.
3.3.2.3 Gbus Space The Gbus is the collective term for the FEPROMs, console UARTs, watch chip, and module registers. All Gbus registers are 1-byte wide, addressed on 64-bytes boundaries. Figure 3-4 shows how local Gbus space registers are assigned.
3.4 CPU Module Window Space Support CSRs that exist on some external I/O buses are accessed through window space transactions. Rather than issuing a read command and waiting for data to be returned to the CPU module from an external I/O bus, the CPU module and I/O port have a protocol to permit disconnected reads. This allows a CPU module to access external I/O CSRs without holding the bus for long periods of time.
Table 3-4 Decrement Queue Counter Address Assignments I/O Port Slot Address Designation 4 5 6 7 8 BSB+400 BSB+440 BSB+480 BSB+4C0 BSB+500 TLWSDQR4 - Window Space DECR Queue Counter for slot 4 TLWSDQR5 - Window Space DECR Queue Counter for slot 5 TLWSDQR6 - Window Space DECR Queue Counter for slot 6 TLWSDQR7 - Window Space DECR Queue Counter for slot 7 TLWSDQR8 - Window Space DECR Queue Counter for slot 8 For window space reads, the I/O port issues the write to the Decrement Queue Counter as soon as
Table 3-5 PCI Address Bit Descriptions Name Bit(s) Function IO_SPACE <39> DECchip 21164 I/O space if set to 1.
data issued by DECchip 21164 is transmitted on the TLSB, along with all the INT4 mask bits. The I/O port pulls the appropriate longword out of the 32-byte block and packages it, along with address bits <4:3>, into a Down Hose packet. Note that on sparse writes, the I/O port generates the <4:3> value. These bits are driven as 00 by the CPU module. The appropriate longword is selected by the state of bits <4:3>.
Dense PCI memory space is longword addressable only. You cannot write to individual bytes. You must do longword writes. You can do quadword writes using the STQ instructions, if you want. To get at individual bytes, you must use the sparse space access method. Writes to dense PCI memory space will be merged up to 32 bytes and performed in one PCI transaction to the extent that the PCI target device can deal with writes of this size.
are reported to DECchip 21164 through system machine check interrupts (IPL 1F hex - SYS_MCH_CHK_IRQ). The interrupt causes the DECchip 21164 to vector to the SCB system machine check entry point (offset 660 hex) when DECchip 21164’s IPL drops below 1F hex and DECchip 21164 is not in PAL mode. Hard errors may be either data or address related. The detection of data related hard errors causes the CPU module to assert TLSB_DATA_ERROR. The detection of the other hard errors has no effect on TLSB_DATA_ERROR.
3.5.1.
3.5.2.1 Transmit Check Errors A node must check that its bus assertions get onto the bus properly by reading from the bus and comparing it to what was driven. A mismatch can occur because of a hardware error on the bus, or if two nodes attempt to drive the fields in the same cycle. A mismatch results in the setting of a bit in the TLBER register and the assertion of TLSB_FAULT.
3.5.2.3 No Acknowledge Errors Whenever a commander node expects but does not receive an acknowledgment of its address transmission as an assertion of TLSB_CMD_ACK, it sets an error bit in its TLBER register. For memory space accesses that are not acknowledged, is set: for CSR accesses, is set. The exception to this rule is a CSR write to I/O mailbox registers; no acknowledgment is not regarded as an error.
3.5.4 Multiple Errors The error registers can only hold information relative to one error. It is the responsibility of software to read and clear all error bits and status. Even when errors occur infrequently there is a chance that a second error can occur before software clears all status from a previous error. The error register descriptions specify the behavior of a node when multiple errors occur. Some errors are more important to software than others.
Chapter 4 Memory Subsystem The memory subsystem consists of hierarchically accessed levels that reside in different locations in the system. The memory hierarchy consists of three main parts: • Internal Caches - These caches reside on the DECchip 21164. • Backup Cache - This cache is external to the DECchip 21164 and resides on the CPU module. • Main Memory - Consists of one or more memory modules. 4.
4.1.3 Second-Level Cache The second-level cache (S-cache) is a 96-Kbyte, 3-way set associative, physically addressed, write-back, write-allocate cache with 32- or 64-byte blocks (configured by SC_CTL; see DECchip 21164 Functional Specification). It is a mixed data and instruction cache. The Scache is fully pipelined. If the S-cache block size is configured to 32 blocks, the S-cache is organized as three sets of 512 blocks where each block consists of two 32-byte subblocks.
4.2.2 B-Cache Tags Many locations in memory space can map onto one index in the cache. To identify which of these memory locations is currently stored in the B-cache, a tag for each block is stored in the tag address RAMs. This tag together with the B-cache index uniquely identifies the stored block. The tag address is stored in the tag RAMs with odd parity.
Figure 4-3 Cache Index and Tag Mapping to Block Address (16MB) 39 38 6 5 4 Processor Byte Address 0 24 23 38 Tag<38:24> 6 B-Cache Index<23:6> Wrap Order BXB0822.AI 4.2.3 Updates and Invalidates If a block is shared, and a CPU wants to write it, the write must be issued on the TLSB. Writes of a shared block cause the block to be invalidated in the cache of all CPUs other than the one that issued the write. 4.2.
Table 4-1 V B-Stat S D B-Cache States State of Cache Line Assuming Tag Match 0 X X Cache miss. The block is not present in the cache. 1 0 0 Valid for read or write. This cache line contains the only cached copy of the block. The copy in memory is identical to this block. 1 0 1 Valid for read or write. This cache line contains the only cached copy of the block. The contents of the block have been modified more recently than the copy in memory. 1 1 0 Valid block.
• State transition due to TLSB activity Table 4-3 shows how the cache state can change due to bus activity. TLSB writes always clean (make nondirty) the cache line in both the initiating node and all nodes that choose to take the update. They also update the appropriate location in main memory. TLSB reads do not affect the state of the Dirty bit, because the block must still be written to memory to ensure that memory has the correct version of the block. 4.2.
Table 4-2 State Transition Due to Processor Activity Processor Request Tag Probe Result Action on TLSB TLSB Response Next Cache State Read Invalid Read ______ Shared Read Invalid Read Write2 Invalid Read Shared ______ Shared Write2 Invalid Read Shared ______ _____ Shared, Dirty _____ Shared, Dirty ______ Shared, Dirty _____ Shared, Dirty Read ______ Shared Read Read Write2 Write2 1 _____ _____ Match AND Dirty _____ _____ Match AND Dirty _____ _____ Match AND Dirty _____ _____ Matc
Table 4-3 TLSB Operation State Transition Due to TLSB Activity Tag Probe Result Module Response Read _____ Match OR Invalid _____ Match OR Invalid _____ Match AND Dirty ______ _____ Shared, Dirty ______ _____ Shared, Dirty _____ Shared, Dirty Read Match AND Dirty Shared, Dirty Shared, Dirty Write Match ______ _____ Shared, Dirty Invalid Read Write 1 Next Cache State Comment No change No change _____ Shared, Dirty This module must supply the data.
the write must be reissued by the DECchip 21164 to the TLSB as a Write Block. In the case that the Set Dirty bit is held off by an invalidate to the block, the Set Dirty request is reissued as a Read-Miss-Modify. To perform a write to a shared block, DECchip 21164 issues a Write Block request. The CPU module arbitrates for and acquires the bus before acknowledging the Write Block. By acquiring the TLSB before acknowledging the Write Block command, the write is guaranteed to be completed in order.
During memory writes, TLSB memory modules store write data and ECC check bits as they are received off the TLSB. A minor modification of the ECC check bits is done before they are written to the DRAMs to allow for the addition of a row parity bit and a column parity bit to provide additional data integrity protection. During memory reads, memory modules strip off the encoded Row/Col parity bits from the ECC check bits prior to asserting the read data and check bits onto the TLSB. 4.3.
4.3.1.1 Control Address Interface The control address interface (CTL) is a single gate array. It provides the interface to the TLSB, controls DRAM timing and refresh, runs memory self-test, and contains some of the TLSB and memory-specific registers. CTL decodes the TLSB command and memory bank in the case of memory reads and writes, or the TLSB address during CSR operations to determine if it is selected for this transaction.
DRAM arrays. The MDI includes data buffers, ECC checking logic, selftest data generation and checking logic, and CSRs. MDI concatenates two 72-bit TLSB transfers into one 144-bit transfer to the DRAMs during memory writes. During memory reads, 144-bit reads from the DRAMs are issued onto the TLSB via two 72-bit consecutive transfers.
four memory modules, with at least two strings each, supports a maximum of 8-way interleaving. 4.3.2 Memory Organization The physical memory composed of a single or multiple memory modules can be organized in various ways to optimize memory access. Memory can be configured with MS7CC modules of various capacities, from 128 Mbytes to 2 Gbytes. The DRAM arrays consist of DRAMs, control signals, and address buffer components. The memory modules can use DRAM sizes of 4 Mbits or 16 Mbits.
Figure 4-5 Two-Way Interleave of a 128-Mbyte DRAM Array Bank 0 Bank 1 0000 0000 0000 0040 0000 0080 0000 00C0 64 Mbytes 64 Mbytes 07FF FF80 07FF FFC0 Block size = 64 Bytes DRAM size = 4 Mbits Memory Capacity = 128 Mbytes BXB-0307A-92 Memory modules of different capacities can be interleaved as a set with modules of another capacity. For example, two 128-Mbyte modules can be interleaved with a single 256-Mbyte module as one set that is 4-way interleaved.
module can result in reduced system throughput due to common data path contention between the two banks. At the module level, the DRAM arrays can be interleaved on 64-byte block boundaries. The DRAM array in a 2-string MS7CC memory module is always interleaved. In multimodule memory subsystems, three modes of interleave are possible at the system level: default, explicit, and none. The interleave mode selection parameters are stored in the console FEPROM and can be modified through the console program.
group of DRAM arrays. The default mode optimizes interleaving of memory in any arrangement of memory modules. If the FEPROM specifies explicit interleave sets, the console then interleaves the arrays as requested. In a noninterleave mode, the console configures arrays in order, by node number, with the lowest numbered array at the lowest physical address. 4.3.3 Refresh Each module implements CBR (CAS Before Ras) DRAM refresh.
sole to locate and map out bad areas of physical address space. Self-test is invoked during system power-up, when a TLSB reset occurs, or by writing to the appropriate CSRs. Two versions of self-test are supported. A normal self-test that runs upon power-up/reset and tests the module rapidly and completely with "pseudorandom" data and address patterns. The test ensures detection of failures prior to booting an operating system.
To exercise the array at its maximum operating speed, banks 0 and 1 are always interleaved during self-test if the module contains more than one string of DRAMs. NOTE: Bank 0 contains the even numbered strings; Bank 1 contains the odd numbered strings. 4.3.6.2 Self-Test Error Reporting Self-test uses three registers to report errors. Table 4-6 shows which registers function in each test mode.
NOTE: Successful execution is not a measure of the array integrity. It indicates that every location in memory space has been tested and written with good or bad ECC. If node reset occurs during self-test, the array will be left in an unknown state. Unlike TLSB reset, node reset does not initiate self-test. 4.3.6.
Table 4-8 Self-Test Times: Moving Inversion, No Errors Found Module Capacity (Mbytes) 128 256 512 1024 2048 1 NA = Not applicable 4-20 Memory Subsystem Test Time (minutes) 4 Mbit DRAM 16 Mbit DRAM .7 1.4 2.7 N/A N/A N/A1 1.4 2.7 5.3 10.
Chapter 5 Memory Interface The memory interface to the TLSB consists of three parts: • Control address interface • Memory data interface • CSR interface 5.1 Control Address Interface The control address interface (CTL) is the primary controller chip for the TLSB memory. It receives the address and control signals from the TLSB and generates the DRAM address and control signals in response to them.
5.1.1.1 Memory Bank State Machine The CTL contains two TLSB control state machines, one for each memory bank. The state machines receive/generate information from/to the TLSB bus as well as other TLSB support logic and DRAM control logic. Each state machine begins operation when a valid TLSB transaction request destined for the particular memory bank that it supports is received. Each state machine has two basic flows, one for memory reads and one for memory writes.
command is one of the factors in determining if the command is acknowledged (TLSB_CMD_ACK) by this node. Table 5-1 shows the encoding of TLSB commands. Table 5-1 5.1.1.
received from the TLSB bus. TLSB_SEND_DATA is also used to check for proper bus sequencing. Note that the TLSB_CMD_ACK and TLSB_SEND _DATA may be issued simultaneously for write transactions by the memory module on an idle TLSB bus. The CTL maintains sequence number registers for each memory bank as well as for CSR transactions. Whenever a command/address request is received, the corresponding address sequence number is stored in the register allocated to the particular bank along with a valid bit.
• Write • Refresh The TLSB memory is designed to operate within the following TLSB clock cycle times: • 10.0 to 11.299 ns • 11.3 to 12.999 ns • 13.0 to 15.0 ns (Memory can operate at cycle times as slow as 30 ns using power-up default settings without violating the DRAM refresh requirements.) To support operating at multiple cycle times while maintaining low latency and high bandwidth, the DSMs are designed as variable-length state machines with multiple taps for controlling external events.
Table 5-2 Two Strings—128MB/512MB Row/Column Address Bit Swapping DRAM Type No.
Table 5-3 Four Strings—256MB/1024MB Row/Column Address Bit Swapping DRAM Type No.
Table 5-4 Eight Strings—512MB/2048MB Row/Column Address Bit Swapping DRAM Type No.
5.2 Memory Data Interface The memory data interface (MDI) is comprised of four chips connected to the DRAM array on one side and to the TLSB bus on the other. The MDI contains the following logic elements: • Data path logic • Write data input logic • Read data output logic • Error detection and correction logic 5.2.1 Data Path Logic The MDI data path provides an interface between the TLSB data path and the DRAM array tri-state bus.
Figure 5-1 64-Bit ECC Coding Scheme DATA BITS 6666 3210 5555 9876 XOR S7 XOR S6 XOR S5 XOR S4 0000 1111 1111 1100 0000 1111 1111 0000 1111 0000 0000 1111 1111 0000 0000 1100 1111 0000 1111 1100 1111 0000 1111 0000 XNOR S3 XNOR S2 XOR S1 XOR S0 0011 1010 0001 1011 1000 01100101 0100 1110 1001 0101 1101 0011 1001 0111 0001 0011 1010 0001 1011 1000 0110 0101 0100 HEX SYNDROME 7766 6666 50DB 8742 CHECK BITS 7654 3210 XOR S7 XOR S6 XOR S5 XOR S4 1000 0100 0010 0001 0000 0000 0000 0000
5.2.2.5 Write Data Out Selection A 2:1 multipexer and a tristate enable capability are provided for interfacing the write data buffers to the DRAM array bus. The multiplexer allows the selection of data from either the bank 0 or the bank 1 buffers. The tristate enable capability allows the write data output to the DRAM array bus to be disabled so that it may be used for receiving read data. 5.2.
on all CSR reads from memory. The ECC bits are generated across bits <63:0> and transmitted on TLSB_ECC<7:0>. 5.2.4 MDI Error Detection and Correction Logic The four MDIs monitor the data received from the TLSB for write data errors. They also monitor read data for ECC errors after it has been transmitted onto the TLSB. Table 5-5 summarizes the errors detected by each of the four MDIs.
in these bits. This field is undefined when either CRECC, CWECC, or ECC is zero. 5.3 CSR Interface The CSR interface, used to transfer the appropriate CSR information between the CTL and the four MDI chips consists of an 8-bit data bus with parity and a command timing signal. The CSR interface manages the transfer of control and status information between the TLSB bus and the TLSB accessible memory module registers.
5.3.1.1 • Multiplexing of local CTL CSRs and the data bytes within them • Byte-wide parity generation and checking of the CSRCA bus TLSB CSR Control The TLSB CSR control monitors the TLSB bus for either a CSR read or a CSR write command destined for that particular node. The TLSB CSR TLSM sequences the TLSB bus by issuing the TLSB_CMD_ACK, TLSB_SEND_DATA, and sequence number at the appropriate time. It is similar to the memory bank state machines.
The memory adapter supports TLSB broadcast writes to its MCR register at address location BSB+1880 (byte address). This allows for the DRAM timing rates, accessed through the MCR register to be written simultaneously, thereby ensuring simultaneous refresh of all memory modules. Since the commander initiating the broadcast write issues both the TLSB_CMD_ACK and TLSB_SEND_DATA for the transaction, this is the only transaction for which the memory adapter may issue TLSB_HOLD.
onto the CSRCA bus during a read of one of its internal CSRs. During a write command to one of the CTL’s CSRs, a LD_EN signal from the sequencer is used to enable data from the CSRCA bus into the proper CSR. Note that the LD_EN signal occurs on the last cycle of each of the four data byte transfers. 5.3.1.3 CSR Multiplexing The CTL contains two MUXes used to multiplex the appropriate CSR data onto the CSRCA bus during a CSR read of an internal register.
Table 5-7 CSRCA Data Bus Master Chip Select Read/Write CSRCA Driver 1XX - CTL 011 - MDI3 010 - MDI2 001 - MDI1 000 - MDI0 1XX - CTL 011 - MDI3 010 - MDI2 001 - MDI1 000 - MDI0 Read Read Read Read Read Write Write Write Write Write CTL MD13 MD12 MD11 MD10 MD10 MD10 MD10 MD10 MD130 For a read command, the selected chip drives the appropriate data on the CSRCA bus. Each of the MDI chips receives the data and loads it into its Merge register.
5.3.2.4 CSRCA Parity The CSRCA bus is protected by byte-wide odd parity. All data transmitted over this bus is accompanied by a valid parity bit (CSRCA<8>) to be checked against the data by all chips. Parity errors on the CSRCA bus during CSR read transactions cause Unpredictable data to be returned to the TLSB bus. Receiving data with bad ECC from the TLSB on CSR write transactions causes the CSRCA parity bit to be inverted, forcing bad parity.
Chapter 6 I/O Port The I/O port is the interface of the I/O subsystem to the TLSB bus. Two modules can be used for I/O operations: KFTHA and KFTIA (integrated I/O port). Figure 6-1 shows the I/O subsystem block diagram with a KFTHA module. NOTE: The term "I/O port" applies to both modules, KFTHA and KFTIA. A specific I/O module is referred to by its name.
The I/O port interfaces the TLSB bus to up to four different I/O buses through separate I/O bus adapter modules. Digital provides three types of I/O adapters: • XMI bus adapter—DWLMA • Futurebus+ adapter—DWLAA • PCI bus adapter—DWLPA (EISA bus through a bridge on the PCI bus) 6.1 Configuration Node 8 of the TLSB is dedicated to the I/O port. Nodes 4, 5, 6, and 7 can also be configured for I/O. The I/O port at node 8 arbitrates for the TLSB bus using a dedicated high/low priority protocol.
The two Up Hose HDRs receive packets from the four Up Hoses (two hoses per HDR) and transmit them to the IDRs through the Turbo Vortex bus. The other two Down Hose HDRs receive packets from the IDRs through the Turbo Vortex bus and transmit them to the four Down Hoses (two hoses per HDR). Figure 6-2 shows the major blocks of the KFTHA module.
mation between the TLSB and I/O adapter modules by transmitting and receiving packets across the hose(s). Mailbox, I/O window, device interrupt, DMA read/IREAD, and NVRAM write transactions (see following subsections) consist of packet pairs: a command packet and a status return packet. • The mailbox transaction consists of a Mailbox Command packet and a Mailbox Status Return packet. • Window read transactions are made up of window read command packets followed by window read data return packets.
Table 6-1 I/O Port Transaction Types Transaction Initiator TLSB Commands Hose Packets CSR read CPU CSR read None - local I/O port registers CSR write CPU CSR write None - local I/O port registers Window read CPU CSR read, CSR write Window read cmd, win rd data ret Window write CPU CSR write Window wr cmd, win wr status ret Mailbox CPU CSR write, read, write Mailbox cmd, Mailbox status ret DMA read I/O device Read DMA read, DMA read data return I/O device Write DMA unmasked wr
The I/O port can support up to 16 CPU chips. However, if more than four CPU chips are present, any additional CPU chip must share a TLMBPR register pair with another CPU chip. CAUTION: If two CPUs are sharing a common TLMBPR, there is a slight possibility that one of the CPUs could continually win access to that TLMBPR, thus causing the other CPU to be locked out of ever gaining access to it.
6.3.2 I/O Window Space Transactions CSRs that exist on some external I/O buses are accessed through I/O window space transactions. One such external I/O bus is the PCI. NOTE: Refer to the DWLPA PCI Adapter Technical Manual for further discussion of transactions on the PCI bus and addressing of PCI devices. When a CPU chip wants to read or write a location on one of these external I/O buses, it issues a CSR read command or a CSR write command on the TLSB, along with the address of the target location.
6.3.2.2 CSR Read Transactions to I/O Window Space A CSR read command to node 4 through 8 I/O window space causes an I/O port installed in that node to assemble a window read command packet (sparse or dense, depending on the type of transaction) and transmit it on the Down Hose. The I/O port returns Unpredictable data to the TLSB commander node.
Therefore, when an interrupt occurs on an I/O bus (that is, XMI, Futurebus+, or PCI), the I/O bus adapter must first acquire the interrupt vector for that interrupt. On the Futurebus+ and the PCI, the vector is acquired as part of the INTR transaction. On the XMI bus, the vector is acquired using an IDENT transaction. If the interrupt was a WE (write error) IVINTR, the XMI adapter module uses a predefined vector instead of executing an IDENT.
• I/O port generated error interrupts transmit a special vector on the TLSB, which must be preloaded by system software into the I/O port Interrupt Vector Register (TIVR) at system initialization. • The I/O port has a special I/O port interrupt mask bit, , that must be loaded by software at system initialization. causes all I/O port specific generated error interrupts to be enabled/disabled (for example, TLSB ECC error, hose parity error, and so on).
DMA IREAD command, the XMI I/O adapter acknowledges the IREAD and pends the transaction. This frees the XMI for other bus traffic. The XMI I/O adapter then transmits a quadword-aligned DMA IREAD request packet to the I/O port on the Up Hose. Included in the DMA IREAD request packet is the target TLSB address, a tag field to allow the XMI I/O adapter to associate the DMA IREAD request with the DMA return data packet, and the length code indicating the amount of data requested.
requires a single TLSB bus write transaction and is always a double hexword. A DMA write request packet is executed as a disconnected (write-and-run) operation and therefore has no status return packet associated with it. Once the I/O bus adapter transmits the DMA write request packet over the Up Hose, the transaction is complete. 6.3.6.1 DMA Unmasked Write The DMA unmasked write packet is the most efficient DMA write that the I/O port supports.
detected on the Up Hose (for example, a parity error or sequence error), or if the TLSB bus Read-Modify-Write operation is unsuccessful, the I/O port logs the error and generates an error interrupt to the CPU(s). 6.3.7 Extended NVRAM Write Transactions The Memory Channel write transaction is used to deliver a block of data, along with its TLSB physical address, to the remote I/O bus. This transaction is used to support Prestoserve NVRAM writes.
When an I/O port receives a window write status return packet on the Up Hose, it decrements its remote adapter node buffer counters and discards the packet. If the Memory Channel write address range does not fall within the range of an associated valid outgoing Down Hose Range register, the I/O port discards the transaction and sets ICCNSE<3> (Memory Channel nonexistent memory error). The I/O port then generates an interrupt on IPL 17, if the ICCNSE<31> (interrupt enable) is set and ICCMSR<5> is clear. 6.
must not overwrite a mailbox that is still in use ( not set by the I/O port). The I/O system architecture requires that there be only a single softwarevisible mailbox pointer CSR (TLMBPR) address. Once the software has built a mailbox structure in main memory, it loads the I/O port’s TLMBPR register with the double hexword aligned address of the mailbox. There are eight TLMBPR registers in the I/O port supporting four CPU chips.
Figure 6-3 Sparse Address Space Reads TLSB_BANK_NUM <3:0> 3 2 1 0 VID TLSB_ADR<39:0> 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 2019 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 Byte-Aligned I/O Address <4:3> Byte Length Field <31:5> Byte-Aligned I/O Address <26:0> <33:32> Space Select Field 01 = Sparse memory space 10 = Sparse I/O space 11 = Sparse configuration space <35:34> Hose number in port being addressed (0 - 3) <38:36> TLSB Responder Node 0 - 4 Nodes 4 - 8 I/O window sp
Table 6-3 Sparse Address Space Read Field Descriptions Field Description TLSB_BANK_NUM<3:0> Contains the TLSB commander virtual ID (VID). TLSB_ADR<39> Indicates the address is an I/O address space reference. It will always be a one if the reference is in I/O address space.
Figure 6-5 Sparse Address Space Writes TLSB_BANK_NUM <3:0> 3 2 1 0 VID TLSB_ADR<39:0> 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 2019 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 Byte-Aligned I/O Address 0 <31:5> Byte-Aligned I/O Address <26:0> <33:32> Space Select Field 01 = Sparse memory space 10 = Sparse I/O space 11 = Sparse configuration space <35:34> Hose number in port being addressed (0 - 3) <38:36> TLSB Responder Node 0 - 4 Nodes 4 - 8 I/O window space, resp.
Table 6-4 Sparse Address Space Write Field Descriptions Field Description TLSB_BANK_NUM<3:0> Contains the TLSB commander virtual ID (VID). TLSB_ADR<39> Indicates the address is an I/O address space reference. It will always be one if the reference is in I/O address space.
Table 6-5 Sparse Address Write Length Encoding Valid Bits <6,4,2,0> Length <1:0> TLSB Quadword Transmit on Hose 0001 001X 01XX 1XXX 00 01 10 11 63–0 (QW 0) 127–64 (QW 1) 191–128 (QW 2) 192–255 (QW 3) NOTE: The byte-length code is transmitted on the hose as LEN<1:0>. The Length field is equivalent to TLSB_ADR<4:3> for sparse address space reads. 6.4.3 Dense Address Space Transactions The TLSB protocol is the same for dense address space reads and dense address space writes.
Table 6-6 Dense Address Space Transaction Field Descriptions Field Description TLSB_BANK_NUM<<3:0> Contains the TLSB commander virtual ID (VID). TLSB_ADR<39> Indicates the address is an I/O address space reference. It will always be one if the reference is in I/O address space.
Figure 6-8 256 Dense Address Space Write Data 224 LW 7 192 LW 6 160 LW 5 V6 V7 128 LW 4 96 LW 3 V4 V5 64 LW 2 32 LW 1 V2 V3 CYC 0 LW 0 V1 1 V0 2 TLSB_D<0> TLSB_D<32> TLSB_D<64> TLSB_D<96> TLSB_D<128> TLSB_D<160> TLSB_D<192> TLSB_D<224> BXB0821.AI The returned hexword data for a dense window read command is asserted on the first data word of the CSR write to broadcast space. Figure 6-9 shows the position within the TLSB data word in which the dense read data is returned.
6.5 TLSB Interface All TLSB bus transactions consist of one command/address cycle on the address bus and two data cycles on the data bus. The TLSB bus implements separate address and data buses to reduce memory latency, to allow the TLSB to adapt to different speed memories, and a range of bus cycle times (10 to 30 ns). To create a low latency system, memory is addressed by a unique 4-bit bank number transmitted on the TLSB address bus.
Table 6-7 Transaction Types Supported by the I/O Port TLSB_CMD<2:0> Initiates Responds to Command 0 1 2 3 4 5 6 7 Yes No Yes Yes Yes Yes No1 Yes2 No No No No No No Yes Yes No-op Victim Read Write Read Bank Lock Write Bank Unlock CSR Read CSR Write 1 If the I/O port is in debug mode, it can initiate CSR reads and writes. 2 The I/O port initiates Write Broadcast CSR transactions only (unless in debug mode).
Table 6-8 Wrapped Reads Transaction Length Octaword Octaword Hexword Hexword Double hexword Byte Address <5:0-> 1 0XXXXX 1XXXXX 0XXXXX 1XXXXX XXXXXX Wrapped No Yes No Yes No 1 X = Don’t care. Interlocked Read/Unlock Write Transactions VAX CI-port architecture (VAXport) devices require Interlocked Read (IREAD) and Unlock Write (UWMask) transactions to access shared software data structures.
Modify-Write on the TLSB. The quadword of data that the I/O device sends in the masked write command contains the original data with the correct state of the lock bit, that is, bit <0> is clear. NOTE: There is no support for interlocked commands on the Futurebus+. DMA Unmasked Write Transactions The I/O port supports unmasked double hexword writes to memory. Unmasked writes map directly to block (64-byte) writes on the TLSB.
and so on. Figure 6-10 shows the format of the data used by the I/O port in the CSR write (interrupt) transaction. Figure 6-10 Write CSR (Interrupt) Data Format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD IPL <17:14> 9 8 7 6 5 4 3 2 1 0 CPU Mask BXB0814.AI Only one CSR transaction may be active at a time. Note that there is no TLSB_BANK_AVL signal for CSRs, as it is implied and does not appear on the TLSB bus.
hose). The I/O port, however, could post up to five interrupts to the CPUs at IPL 17 (one per hose plus one I/O port generated error interrupt). When a CPU reads a specific TLILIDx register that contains a valid vector, the I/O port builds an interrupt status return packet and returns it on the appropriate Down Hose to the I/O adapter module. The one exception to this rule is an I/O port internally generated error interrupt for which no interrupt status return packet is required.
in strict first-come, first-served order. Any other writes to the TLMBPR register by a CPU that already has two mailbox transactions pending is NO ACKed. A further constraint is that only one mailbox transaction can be processed by the I/O port at any time. All further mailbox transactions in the TLMBPR queue are put on hold until the previous mailbox transaction completes. Completion of a transaction is signaled by a mailbox status packet returned to the I/O port by an I/O bus adapter.
If the Error bit is set in the window Read Data Return packet, the I/O port generates a TLSB CSR (broadcast) write to the CSR Read Data Return Error Register in CSR broadcast space. Data written is Unpredictable. The flow is the same as in the normal case. Extended NVRAM Write Transactions The I/O port compares all extended NVRAM writes targeted to it against its Down Hose Range registers.
6.5.2.1 Node 8 I/O Port Arbitration Mode Selection Several mode-selectable lockout avoidance algorithms are implemented to guarantee that the node 8 I/O port will eventually allow other nodes to access a given memory bank on the TLSB while allowing software to finetune I/O performance. A commander node is deemed "locked out" if it cannot access a given memory bank for a long period of time. The default "minimum latency" mode guarantees correct TLSB operation with optimal node 8 I/O port performance.
Figure 6-11 Minimum Latency Mode RESET REQ8_HIGH WIN or LOSE or PREQ ELSE WIN Notes: WIN = (GRANT* - NOP) LOSE = (REQ8_LOW * PREQ*-WIN) REQ8_LOW ELSE PREQ(potential request) = (-ARB_SUPPRESS* -BANK_AVL* -REQ8_HIGH* -ARB_CYCLE) BXB0811.AI Note that NEXT_REQ_HI would have become asserted in cycle 6 even if the I/O port did not request the bus in cycles 3–6.
the Write Bank Unlock portion of a Read-Modify-Write operation. Figure 6-13 shows the flow for this arbitration mode. Figure 6-13 Toggle 50% High/50% Low Mode RESET Notes: WIN = (GRANT* - NOP) REQ8_HIGH LOSE = (REQ8_LOW * PREQ*-WIN) WIN or LOSE WIN ELSE PREQ(potential request) = (-ARB_SUPPRESS* -BANK_AVL* -REQ8_HIGH* -ARB_CYCLE) REQ8_LOW ELSE BXB0810.
commands are necessary to ensure an atomic operation and maintain cache coherency. 6.5.2.3 Bank Collision Effect on Priority A bank collision occurs when two commanders request the same bank, the first one wins, the second one gets the bus 2 cycles later and finds that it is not allowed to access that bank. Since it is too late to withdraw the request, a no-op command must be placed on the address bus. Any time a no-op is put on the bus the arbitration is considered false.
6.6 Hose Interface The I/O port communicates with the I/O bus adapters over dual-cable buses. These buses are called hoses. The I/O subsystem architecture supports four separate I/O bus adapters, as shown in Figure 6-1. Each hose consists of two separate unidirectional interconnects: a Down Hose, which transmits command/address and data from the I/O port to the I/O bus adapter module; and an Up Hose, which transmits command/address and data from the I/O bus adapter module to the I/O port.
port receives a Window Status Return packet on the Up Hose, it decrements that hose’s counter. The I/O port does not transmit window read/write command packets on the Down Hose when that hose’s counter equals zero. Thus, the I/O adapter’s Down Hose window FIFO never overflows. DMA Read Data Return packets are a result of DMA read packets transmitted by the I/O adapter on the Up Hose.
6.6.2.1 Sparse Address Mapping A sparse address space uses low-order TLSB address bits to encode the size of the access and its byte offset. The I/O port interprets an Alpha physical address in the window space as: • PA - byte-aligned remote I/O bus address • PA<4:3> - length of the transaction • PA<2:0> - ignored The interpretation of the length field and the number of significant address bits are I/O bus adapter and I/O port dependent.
Table 6-10 Down Hose Signals Signal Description DND<31:0> L Down Data Lines. Asserted by the I/O port. Carry command/address, data, or transaction status information. DNP L Down Parity. Carry odd parity across DND<31:0>. DNDATAVAL L Down Data Valid. This line is asserted by the I/O port for each valid cycle of a Down Hose packet. DNCLK H Down Clock. The clock signal sent by the I/O port to the I/O bus adapter. DECPKTCNT L Decrement Packet Count.
Table 6-12 UPCTL<3:0> Encoding UPCTL<3:0> Meaning First Hose Cycle of a Packet Packet Type1 0001 0010 0100 0101 0111 1000 1100 1101 1110 DMA Read IREAD Mailbox Status Return DMA Unmasked Write W/Data DMA Masked Write W/Data INTR/IDENT Window Write Status Dense Window Read Return Sparse Window Read Return Data Cycles of a DMA Masked Write Packet Mask2 0001 0010 0100 1000 1111 UPD<7:0> are valid UPD<15:8> are valid UPD<23:16> are valid UPD<31:24> are valid UPD<31:0> are valid 1 All other UPCTL<3:0> pack
Table 6-13 Hose Status Signals Signals Meaning I/O port interrupts the CPU(s) on the indicated transitions, if interrupts are enabled CBLOK L PWROK H ERROR L X L -> H X I/O adapter just finished powering up - Adapter ready to receive and process packets. I/O port generates interrupt to CPU(s) on transition of PWROK. X H -> L X I/O adapter detected power failure. I/O port generates interrupt to CPU(s) on transition of PWROK. L H H -> L I/O adapter detected a fatal error.
Mailbox Command Packet The Mailbox Command packet is used by processors to access control and status registers in adapters on the XMI and Futurebus+. Status for the Mailbox Command packet is returned in a separate packet on the Up Hose called a Mailbox Status Return packet. Only one Mailbox Command packet can be issued at a time by the I/O port, regardless of the Down Hose for which it is destined.
Table 6-15 Mailbox Command Packet Description Field Description Clock 1, <31:14> Command <31:14> is specific to the remote bus (for example, XMI or Futurebus+) rather than the I/O port, and contains the remote bus operation. It can include fields such as read/write, address only, address width, data width, and so on. Clock 1, <13:12> Command <13:12> bits are forced by the I/O port to indicate a mailbox command packet (for example, 10 bin).
The DMA Read Data Return packet is supported by the Mailbox Only, I/O Window, Full, and Memory Channel variants of the hose protocol. Table 6-16 gives the description of the DMA Read Data Return packet. Table 6-16 DMA Read Data Return Packet Description Field Description Clock 1, <31:24> Tag <7:0> associates the DMA read data return with the corresponding DMA Read packet on the Up Hose. The tag is generated by the I/O bus adapter and sent to the I/O port as part of a DMA Read packet.
DMA Read Data Return packet with the error bit set is returned across the Down Hose. Figure 6-16 DMA Read Data Return Packet with Error DND <31:0> Clock cycle 31 1 24 23 22 TAG <7:0> 14 13 12 11 10 E 0 0 0 0 0 0 0 0 0 0 1 0 8 7 0 LEN 0 0 0 0 0 0 0 0 BXB-0642-93 Table 6-17 gives the description of the DMA Read Data Return packet with error.
not return an INTR/IDENT Status Return packet. Figure 6-17 shows the INTR/IDENT Status Return packet. Figure 6-17 INTR/IDENT Status Return Packet DND <31:0> Clock cycle 31 20 0 0 0 0 0 0 0 0 0 0 0 1 19 16 IPL 15 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 BXB-0643-93 Table 6-18 gives the description of the INTR/IDENT Status Return packet. Table 6-18 INTR/IDENT Status Return Packet Description Field Description Clock 1, <31:20> Are always zero.
Table 6-19 Sparse Window Read Command Packet Description Field Description Clock 1, <31:30> Are always zero. Clock 1, <29:26> Virtual ID of the TLSB commanding node. The VID indicates which CPU is requesting the data. The VID is returned on the Up Hose in all window return data/status packets so that the I/O port can target the requesting commanding node with the data or status of the transaction. Clock 1, <25:15> Are always zero. Clock 1, <14> Indicates read/write: 0 is read, 1 is write.
Figure 6-19 Sparse Window Write Command Packet Clock cycle DND <31:0> 31 30 29 1 0 0 26 25 VID 15 14 13 12 11 Zero 1 1 1 2 Byte Aligned Address <31:0> 3 Data Longword 0 4 Data Longword 1 4 Zero 3 2 1 0 LEN SPC BXB-0570-94 Table 6-20 gives the description of the Sparse Window Write Command packet. Dense Window Read Command Packet The Dense Window Read Command packet is used by processors to read memory space in adapters on remote I/O buses that support direct I/O window space.
Table 6-20 Sparse Window Write Command Packet Description Field Description Clock 1, <31:30> Are always zero. Clock 1, <29:26> Virtual ID of the TLSB commanding node. The VID indicates which CPU is requesting the data. The VID indicates which CPU is requesting the data. The VID is returned on the Up Hose in all window return data/status packets so that the I/O port can target the requesting commanding node with the data or status of the transaction. Clock 1, <25:15> Are always zero.
Table 6-21 Dense Window Read Command Packet Description Field Description Clock 1, <31:30> Are always zero. Clock 1, <29:26> Virtual ID of the TLSB commanding node. The VID indicates which CPU is requesting the data. The VID is returned on the Up Hose in all window return data/status packets so that the I/O port can target the requesting commanding node with the data or status of the transaction. Clock 1, <25:15> Are always zero. Clock 1, <14> Indicates read/write: 0 is read, 1 is write.
Figure 6-21 Dense Window Write Command Packet Clock cycle DND <31:0> 31 30 29 1 0 0 26 25 VID 15 14 13 12 11 Zero 1 1 1 2 Byte Aligned Address <31:0> 3 Byte Mask Bits <31:0> 4 Data Longword 0 5 Data Longword 1 6 Data Longword 2 7 Data Longword 3 8 Data Longword 4 9 Data Longword 5 10 Data Longword 6 11 Data Longword 7 2 Zero 1 0 SPC BXB-0568-94 Table 6-22 gives the description of the Dense Window Write Command packet.
Table 6-22 Dense Window Write Command Packet Description Field Description Clock 1, <31:30> Are always zero. Clock 1, <29:26> Virtual ID of the TLSB commanding node. The VID indicates which CPU is requesting the data. The VID is returned on the Up Hose in all window return data/status packets so that the I/O port can target the requesting commanding node with the data or status of the transaction. Clock 1, <25:15> Are always zero. Clock 1, <14> Indicates read/write: 0 is read, 1 is write.
Figure 6-23 Memory Channel Write Packet Clock cycle DND <31:0> 31 30 29 1 0 E 16 15 14 13 12 11 10 11110 Zero LEN 2 Byte Aligned Address <31:0> 3 Data Longword 0 4 Data Longword 1 5 Data Longword 2 6 Data Longword 3 7 . . Data Longword 4 16 Data Longword 13 17 Data Longword 14 18 Data Longword 15 8 0 7 ADR<39:32> . . BXB-0831-94 Table 6-23 gives the description of the Memory Channel Write packet. 6.6.4.
Table 6-23 Memory Channel Write Packet Description Field Description Clock 1, <31> Always zero. Clock 1, <30> Error. Always sent as zero by the I/O port. Clock 1, <29:16> Are always zero. Clock 1, <15:11> Command field. It is always set to a code of 11110 by the I/O port to indicate a Memory Channel Write packet. For this packet bit <14> is always one. Clock 1, <10:8> Length field.
Table 6-24 Mailbox Status Return Packet Description Field Description Clock 1 and 2, <31:0> The return data longword 0 and 1 fields, respectively. The return data fields contain read data in response to Mailbox Command packets that were reads. This data is Unpredictable when responding to Mailbox Command packets that were writes. Clock 3, <31:2> Device specific field <29:0>. The device specific field contains operation completion status.
Table 6-25 DMA Read Packet Description Field Description Clock 1, <31:24> The TAG<7:0> field allows the subsequent DMA Read Data Return packet on the Down Hose to be associated with a DMA Read Data packet on the Up Hose. The tag is generated by the I/O bus adapter. Clock 1, <23:11> Are always zero. Clock 1, <10:8> The length field indicates the length of the DMA read packet. A DMA read packet has three possible packet lengths: octaword, hexword, and double hexword.
Figure 6-26 Interlock Read Packet UPD <31:0> UPCTL 31 24 23 TAG<7:0> 1* 11 10 0 8 LEN 7 0 ADR <39:32> ADR <31:0> 2 3 0 0 0 1 0 x x x x * = hose cycle BXB-0640-93 Table 6-27 gives the description of the IREAD packet. Table 6-27 Interlock Read Packet Description Field Description Clock 1, <31:24> The TAG<7:0> field allows the subsequent DMA Read Data Return packet on the Down Hose to be associated with an IREAD packet on the Up Hose. The tag is generated by the I/O bus adapter.
DMA Masked Write with Data The DMA Masked Write Packet is a request on the Up Hose from the I/O bus adapter to the I/O port for a TLSB data write transaction. Any combination of mask bits is allowed. However, the I/O bus adapter may or may not support this capability. A mask bit is set to write the corresponding byte of data. This packet is supported by the Mailbox Only, I/O Window, Full, and Memory Channel variants of the hose protocol. Figure 6-27 shows the DMA Masked Write packet.
Table 6-29 DMA Masked Write Packet Description Field Description Clock 1, <31:24> Don’t Care. These bits, which normally form the TAG field, are don’t care, since DMA Masked Write packets are disconnected and have no corresponding return packet. Clock 1, <23:11> Are always zero. Clock 1, <10:8> The length field indicates the length of the packet. A DMA Masked Write packet has three possible packet lengths: octaword, hexword, and double hexword.
DMA Unmasked Write with Data The DMA Unmasked Write packet is a request on the Up Hose from the I/O bus adapter to the I/O port for a TLSB data write transaction. The data length of the unmasked write is always a double hexword and the LEN code must indicate a double hexword (100). This packet is supported by the Mailbox Only, I/O Window, Full, and Memory Channel variants of the hose protocol. Figure 6-28 shows the DMA Unmasked Write packet.
Table 6-31 DMA Unmasked Write Packet Description Field Description Clock 1, <31:24> Don’t Care. These bits, which normally form the TAG field, are don’t care, since DMA Unmasked Write packets are disconnected and have no corresponding return packet. Clock 1, <23:11> Are always zero. Clock 1, <10:8> The length field indicates the length of the packet. It must have the value of 100 (double hexword).
Table 6-32 INTR/IDENT Status Return Packet Description Field Description Clock 1, <31:24> Don’t Care. These bits, which normally form the TAG field, are don’t care, since only one interrupt per IPL can be pending at a time and the corresponding INTR/IDENT Status Return packet can be easily identified by the IPL field. Clock 1, <23:20> Are always zero. Clock 1, <19:16> The IPL field is the interrupt priority level of the interrupt request. Bits <19:16> correspond to IPL 17 to IPL 14, respectively.
Table 6-33 Sparse Window Read Data Return Packet Description Field Description Clock 1, <31> Is always zero. Clock 1, <30> Error. Set by the remote I/O bus adapter if any errors were detected on the transfer. Clock 1, <29:26> Virtual ID of the TLSB commander node. This enables the I/O port to associate the packet with the originating commander node of the transaction. This field is the same as the VID field in the Down Hose Sparse Window Read Command packet being acknowledged.
Figure 6-31 Dense Window Read Data Return Packet UPD <31:0> UPCTL 31 30 29 28 27 26 25 1* 0 E VID 10 Zero 9 6 5 Count 0 Zero 3 0 1 1 0 1 2 Data Longword 0 x x x x 3 Data Longword 1 x x x x 4 Data Longword 2 x x x x 5 Data Longword 3 x x x x 6 Data Longword 4 x x x x 7 Data Longword 5 x x x x 8 Data Longword 6 x x x x 9 Data Longword 7 x x x x * = clock cycle BXB-0787-94 Table 6-34 gives the description of the dense window read data return packet.
Window Write Status Return Packet The Window Write Status Return packet is used by adapters on remote buses that support I/O window space packets to return the completion status of a previously issued dense/sparse window write command packet. The command field value of the Window Write Status Return packet is C (hex). This packet is supported by the Mailbox Only, I/O Window, Full, and Memory Channel variants of the hose protocol. Figure 6-32 shows the Window Write Status Return packet.
6.6.5 Hose Errors Four types of errors affect the hoses: • Parity errors on the transmitted data/control information • Illegal packet errors • FIFO overflow errors • I/O port internal errors Parity errors are detected on all Up Hoses and have corresponding CSR error bits to indicate the failure to the system. Parity errors cause the I/O port to generate an error interrupt to the appropriate CPU(s) if interrupts are enabled.
6.7 I/O Port Error Handling The I/O port provides a high reliability electrical environment. Consequently, error handling is biased toward detection rather than correction. The I/O port attempts to retain state for system software to determine the severity level and recoverability of any error. However, due to the deep pipelined nature of the protocol, the amount of state saved is limited. The I/O port does not detect errors due to multiple error occurrences. The only exception is the data bus ECC.
If the I/O port detects a hard internal error. it sets the appropriate error bit in either the ICCNSE register or one of the IDPNSEn registers, whichever is applicable. The I/O port then posts an IPL 17 error interrupt to the processor(s) to inform the operating system of the error if interrupts are enabled (ICCNSE set). The action taken on this type of error is determined by the operating system. The following errors leave the I/O port in an Unpredictable state.
Each IDR on the I/O port receives 64 data bits and 8 ECC bits from the TLSB. Error checking is performed and if a data error is detected, the IDR(s) set the appropriate error bit in the TLESRn register. The IDR(s) also informs the ICR that a data error, either hard or soft, has been detected. The ICR asserts TLSB_DATA_ERROR on the TLSB to inform other nodes monitoring the bus that a data error was detected.
another node and ensure that TLSB_FAULT is only asserted for two cycles. When the I/O port detects assertion of TLSB_FAULT on the TLSB, it immediately aborts all outstanding transactions and resets to a known state. The I/O port deasserts its REQUEST signal no later than two cycles from the assertion of TLSB_FAULT. All other TLSB bus signals that the I/O port may have been driving are deasserted within 16 cycles from the assertion of TLSB_FAULT.
Hose PWROK Transitioned and Hose Error are technically hose errors, not internal I/O port errors. However, they are handled by the I/O port in the same manner as internal errors. The posting of IPL 17 error interrupts are enabled by software by setting ICCNSE after a unique interrupt vector for the I/O port has been loaded into the IDR Vector Register. Once enabled, the I/O port posts an IPL 17 interrupt when one of the above error conditions is detected.
The I/O port assertion checks TLSB_CMD_ACK only when it is being asserted by the the I/O port. If the I/O port detects a mismatch, it sets and asserts TLSB_FAULT. The I/O port assertion checks TLSB_ARB_SUP only when it is being asserted by the I/O port. If the I/O port detects a mismatch, it sets and asserts TLSB_FAULT. 6.7.7.2 Address Bus Parity Errors The I/O port monitors the address bus command, bank number, and address fields for correct parity during valid transactions.
tected, the I/O port does not issue the transaction on the TLSB. It simply aborts that transaction by transmitting a UTV_ERROR_A (or B) code across its internal TL_CMD bus to each IDR. The I/O port then posts an IPL 17 interrupt on the TLSB, if enabled by ICCNSE. 6.7.8 Data Bus Errors Data bus errors are either ECC-detected errors on data transfers or control errors on the data bus.
ting . A UECC error causes the I/O port to set TLBER and assert TLSB_DATA_ERROR. An IPL 17 is also posted, if enabled by software. If the error was detected on data that the I/O port was writing to memory, then TLESR and TLBER bits are also set. If the error is detected on a read type instruction, a down Turbo Vortex read return data packet is sent to the HDR. However, each IDR that detected an error asserts the down Turbo Vortex RER signal to the HDR for the duration of the packet.
6.7.8.6 Transmit Check Errors The I/O port level checks the TLSB_D<255:0> and TLSB_ECC<31:0> fields when it is driving data on the TLSB bus. The I/O port sets in its TLESRn register if it detects a mismatch. Since ECC is checked on the data received from the bus, a TCE error usually causes the I/O port to set one of , , or .
• The TLFADRn registers record the address, command, and bank number from the command. These registers can only hold information relative to one error. It is the responsibility of software to read and clear all error bits and status. Even when errors occur infrequently, there is a chance that a second error can occur before software clears all status from a previous error. The error register descriptions specify the behavior of the I/O port when multiple errors occur.
The ICR up Turbo Vortex interface checks for the following types of errors: • Parity errors • Sequence errors • Buffer overflow errors • Illegal command errors Reporting of up Turbo Vortex detected errors can be enabled by setting ICCNSE, which results in the I/O port posting an IPL 17 interrupt. In addition to posting an interrupt, the ICR transmits a UTV_ERROR_A (or B) command across the I/O port’s internal command bus to each of the IDRs.
assertion of this signal causes ICCNSE to set. An IPL 17 interrupt will also be posted if ICCNSE is set. When the down HDR completes processing of the failing packet, it attempts to assert DECR_PKT to the ICR gate array. DECR_PKT is only asserted if a packet was sent down the hose (for example, DMA read return with error packet). This keeps the buffer counters in sync across the two chips.
serts TLSB_FAULT. The catastrophic failure requires a reset of the I/O port to return the I/O port to a known state. 6.7.11.4 Hose Status Change Errors The IDPNSEn registers contain status information relating to the ability of the I/O adapter to receive commands and data from the Down Hose. These bits are and . Either a high-to-low or a low-to-high transition of HOSEn_PWROK causes an IPL 17 interrupt to be posted, if ICCNSE is set.
• One external hose connection • Optional multimode FDDI daughter card or UTP FDDI daughter card • Optional 4-Mbyte NVRAM daughter card • Onboard 128-Kbyte map RAM The integrated I/O port is comprised of two sections, as shown in Figure 6-34.
supports one Turbo Vortex bus (Turbo Vortex Bus A) and two hose buses: internal hose (Hose 0) and external hose (Hose 1). The integrated I/O section contains all the hardware that connects from the internal hose, including the two HPC (hose to PCI) gate arrays, to all the SCSI, Ethernet, and FDDI and NVRAM daughter cards (Figure 6-35). The integrated I/O section is a logically separate I/O subsystem connected to the integrated I/O port interface through the internal hose.
Figure 6-35 Integrated I/O Section of the KFTIA PCI 1 Down Hose Interface HPC 1 DC287 Up 10BaseT QLogic ISP 1020 FNS QLogic ISP 1020 FWD Ethernet 1 SCSI 3 SCSI 2 NVRAM Card PCI 1 PCI 0 FDDI Card HPC 0 DC287 Control and Map RAM PCI 0 6.8.1.1 Multimode or UTP FDDI 10BaseT Ethernet 0 QLogic ISP 1020 FWD SCSI 1 QLogic ISP 1020 FWD SCSI 0 BXB0792.AI PCI Interface The PCI interface provides a host bridge to two physical PCI buses.
The PCI interface consists of the following sections: • Two HPC (hose to PCI) gate arrays • Map RAM • Up Hose control logic These sections are discussed below. HPC Gate Arrays Each HPC provides the connection between the internal hose and each PCI bus (PCI0 and PCI1). The HPCs provide access to all three PCI address spaces: memory space, I/O space, and configuration space. All three are accessible using sparse address mapping that allows for individual byte access.
6.8.1.3 Ethernet Ports The integrated I/O port supports two Ethernet ports and uses the twistedpair (10baseT) connection. The Ethernet port can sustain reception of back-to-back packets at full line speed with a 9.6 µs IPG (interpacket gap), or to transmit such back-to-back packets, due to its on-chip dual 256-byte FIFOs. 6.8.1.4 Optional NVRAM Daughter Card NVRAM is a memory module (DJ-ML300-BA) used on the PCI local bus, which provides for the retention of data in the event of system failure.
6.8.2.2 Mailbox Transaction All mailbox transactions are executed by the HPC as a PCI master. Mailbox transactions forwarded from the HDR can access a PCI I/O device through the PCI bus, an HPC CSR, or the map RAM. Mailbox transactions to PCI memory or I/O space on the PCI bus are sent to both PCI buses. However, only one bus responds to the transaction. Mailbox transactions are byte, word, tribyte, longword, or quadword in length. A Mailbox Command packet is received by the HPC on the Down Hose.
rupt’s vector and merging it with a programmable device IPL. The INTR/IDENT is then sent to the HDR over the Up Hose. Because the interrupt request lines of the devices are connected to more than one of the HPC’s 16 interrupt request input pins, software controls the interrupt priority of the devices on each PCI bus. See Table 6-36.
Chapter 7 System Registers The system registers are divided into two main groups: • TLSB registers • Node-specific registers TLSB registers are used for internode communications and transactions over the TLSB bus. Node-specific registers implement functions related to the operation of the module. Each node implements some TLSB required registers as well as nodespecific registers. All system registers are located in node spaces and are accessed using CSR read or write commands.
• When the value of a bit position is given explicitly in a register diagram, the information conveyed is as follows: Bit Value Designation Meaning 0 Reads as zero; ignored on writes. 1 Reads as one; ignored on writes. X Does not exist in hardware. The value of the bit is Unpredictable on reads and ignored on writes. • The entry in the type column of a register description table may include the initialization value of the bits.
Table 7-1 TLSB Node Space Base Addresses Node ‘ 0 1 2 3 4 5 6 7 8 Module Physical Base Address (BB) Address Field <39:0> 34-Bit Range CPU, Memory CPU, Memory CPU, Memory CPU, Memory CPU, Memory, I/O CPU, Memory, I/O CPU, Memory, I/O CPU, Memory, I/O I/O FF 8800 0000 FF 8840 0000 FF 8880 0000 FF 88C0 0000 FF 8900 0000 FF 8940 0000 FF 8980 0000 FF 89C0 0000 FF 8A00 0000 System Registers 7-3
7.3 TLSB Registers Table 7-2 lists the TLSB registers. Descriptions of registers follow.
TLDEV—Device Register BB + 0000 R/W Address Access The TLDEV register is loaded during initialization with information that identifies a node. A zero value indicates an uninitialized node. 31 24 23 HWREV 16 15 SWREV 0 DTYPE BXB-0491-93 Table 7-3 TLDEV Register Bit Definitions Name Bit(s) Type Function HWREV <31:24> R/W, 0 Hardware Revision. Identifies the hardware revision level of a TLSB node. The value will be loaded by hardware or self-test firmware during node self-test.
Table 7-3 TLDEV Register Bit Definitions (Continued) Name Bit(s) Type Function DTYPE <15:0> R/W, 0 Device Type. Identifies the type of node as follows: bit <15> specifies a CPU node; bit <14> specifies a memory node; bit <13> specifies an I/O node. Bits <7:0> specify the ID of a node type. The following table defines the current TLSB device types.
TLBER—Bus Error Register Address Access BB + 0040 R/W The TLBER register contains bits that are set when a TLSB node detects errors in the TLSB system. The entire register is locked when the first error bit gets set in this register if TLCNR is set. All bits except the four DSn bits cause the register to be locked. When the register is locked, no bits change value until all bits are cleared by software or TLCNR is cleared. Locking the register is intended only for diagnostics.
Table 7-4 TLBER Register Bit Definitions Name Bit(s) Type Function DTO <31> W1C, 0 Data Timeout. Set when a commanding node times out waiting for a slave to assert TLSB_SEND_DATA. This is a system fatal error that asserts TLSB_FAULT. This error is disabled if TLCNR is set. Memory: Not implemented. DSE <30> W1C, 0 Data Status Error. Set when TLSB_STATCHK does not match the logical OR of TLSB_SHARED and TLSB_DIRTY. This is a system fatal error that asserts TLSB_FAULT.
Table 7-4 TLBER Register Bit Definitions (Continued) Name Bit(s) Type Function DS3 <23> R, U Data Syndrome 3. A status bit set when the TLESR3 register contains status relative to the current data error. This bit is undefined when CRDE, CWDE, and UDE are zero. It is overwritten on a second error of higher significance. DS2 <22> R, U Data Syndrome 2. A status bit set when the TLESR2 register contains status relative to the current data error.
Table 7-4 TLBER Register Bit Definitions (Continued) Name Bit(s) Type Function UDE <16> W1C, 0 Uncorrectable Data Error. Set when is set in any TLESRn register. This is a hard error that asserts TLSB_DATA_ ERROR. CPU: Set when is set in any TLESRn register. I/O: Posts an IPL 17 error interrupt if interrupts are enabled. RSVD <15:11> R, 0 Reserved. Read as zeros. ATDE <10> W1C, 0 Address Transmitter During Error.
Table 7-4 TLBER Register Bit Definitions (Continued) Name Bit(s) Type Function ACKTCE <6> W1C, 0 Acknowledge Transmit Check Error. Set when a transmit check error is detected on the TLSB_CMD_ACK signal. This is a system fatal error that asserts TLSB_FAULT. I/O: Also sets if I/O port was commander of transaction. RTCE <5> W1C, 0 Request Transmit Check Error. Set when a transmit check error is detected on a request signal: TLSB_REQ<7:0>, TLSB_REQ8_HIGH, TLSB_REQ8_LOW.
Table 7-4 TLBER Register Bit Definitions (Continued) Name Bit(s) Type Function BAE <2> W1C, 0 Bank Available Violation Error. Set when a memory bank is addressed by a memory access command while the memory bank is busy. Also set when any node detects a CSR access command while a CSR command is already in progress. This is a system fatal error that asserts TLSB_FAULT. I/O: Also sets . APE <1> W1C, 0 Address Parity Error.
Table 7-4 TLBER Register Bit Definitions (Continued) Name Bit(s) Type Function ATCE <0> W1C, 0 Address Transmit Check Error. CPU: Set when a transmit check error is detected on the TLSB_ADR<39:3>, TLSB_ADR_PAR, TLSB_BANK_NUM<3:0>, TLSB_CMD<2:0>, or TLSB_CMD_PAR signals. This is a system fatal error that asserts TLSB_FAULT. When this bit is set, is also set. Memory: Not implemented.
TLCNR—Configuration Register Address Access BB + 0080 R/W The TLCNR register contains the TLSB system configuration setup and status information. Node-specific configuration information exists in node-specific registers.
Table 7-5 TLCNR Register Bit Definitions Name Bit(s) Type Function LOFE <31> R/W, 0 Lock on First Error. If set, the node locks the TLBER and TLFADR registers when the first error bit is set in the TLBER register. NRST <30> W, 0 Node Reset. When set, the node undergoes a reset sequence. The behavior of a node during reset is implementation specific. CPU: Starts self-test. Caches and CSRs are initialized. Memory: Self-test halts if running and does not restart.
Table 7-5 TLCNR Register Bit Definitions (Continued) Name Bit(s) Type Function STF_B <13> R/W, 1 Self-Test Fail B. When set, indicates that unit has not yet passed self-test. CPU: When set, indicates that CPU1 has not yet passed self-test. Initialized to zero for uniprocessor module. Memory: When set, indicates that memory has not yet completed self-test. Memory clears this bit if self-test executes to completion regardless of whether or not errors were found within the DRAM array.
Table 7-5 TLCNR Register Bit Definitions (Continued) Name Bit(s) Type Function VCNT <11:8> R/W, 0 Virtual Unit Count. This field indicates the number of virtual units contained in this module. CPU: Self-test firmware loads this field with a value of 1 on all uniprocessor modules and 2 on all dual-processor modules. Memory: Memory hardware loads this field with a value of 1 on all single-bank modules, and 2 on all two-bank modules. I/O: I/O port hardware loads a value of 1 to this field.
Table 7-5 TLCNR Register Bit Definitions (Continued) Name Bit(s) Type Function CRDD <1> R/W, 0 Correctable Read Data Error Interrupt Disable. When set, TLSB_DATA_ERROR is not asserted on detection of a single-bit data error during a read command. Setting CRDD in all nodes disables correctable read data error interrupts. CWDD <0> R/W, 0 Correctable Write Data Error Interrupt Disable. When set, TLSB_DATA_ERROR is not asserted on detection of a single-bit data error during a write command.
TLVID—Virtual ID Register BB + 00C0 R/W Address Access The TLVID register contains the TLSB virtual identifiers assigned to a physical node. The virtual units can be CPUs or memory banks. The number of these units is presented in TLCNR. The units are addressed using virtual IDs that are assigned by writing the TLVID register.
Table 7-6 TLVID Register Bit Definitions Name Bit(s) Type Function RSVD <31:8> R/W, 0 Reserved. Must be written as zero. VID_B <7:4> R/W, 0 Virtual ID B. Contains the virtual ID for unit B in this node. Reads zero if unimplemented. CPU: Contains the virtual ID for CPU1. Initializes to TLSB_NID<2:0> shifted left filled with one. A read of this register reads the hardwired value. However, the register must be written to update the DIGA VID field.
TLMMRn—Memory Mapping Registers BB + 0200 to BB + 03C0 W (CPU), R/W (I/O) Address Access The TLMMRn registers contain the mapping information for performing bank decode. 31 26 25 30 12 11 10 9 RSVD 7 6 5 4 3 2 1 0 INTLV ADRMSK ADDRESS VALID 8 SBANK RSVD INTMASK BXB-0757-93 Table 7-7 TLMMRn Register Bit Definitions Name Bit(s) Type Function VALID <31> CPU, W, 0 I/O, R/W, 0 Valid. When set, indicates that the mapping register is valid and can be used in address decoding.
Table 7-7 TLMMRn Register Bit Definitions (Continued) Name Bit(s) Type Function INTLV <10:8> CPU, W, 0 I/O, R/W, 0 Interleave. Lower address bits used in interleaving. This field is compared to physical address lines TLSB_ADR<8:6>. Table 7-8 gives values for various interleave levels. ADRMASK <7:4> CPU, W, 0 I/O, R/W, 0 Address Mask. Indicates the number of address bits not used in the address comparison.
Table 7-9 Address Ranges Selected by ADRMASK Field Values 0 1 2 3 4 5 6 7 8 9 A B C D E F (reserved) Address Range TLSB_ADR Bits Compared TLSB_ADR Bits Masked 64 Mbytes 128 Mbytes 256 Mbytes 512 Mbytes 1 Gbyte 2 Gbytes 4 Gbytes 8 Gbytes 16 Gbytes 32 Gbytes 64 Gbytes 128 Gbytes 256 Gbytes 512 Gbytes 1 Tbyte <39:26> <39:27> <39:28> <39:29> <39:30> <39:31> <39:32> <39:33> <39:34> <39:35> <39:36> <39:37> <39:38> <39> ----- ---<26> <27:26> <28:26> <29:26> <30:26> <31:26> <32:26> <33:26> <34:26>
TLFADRn—Failing Address Registers BB + 0600, 0640 R/W Address Access The TLFADRn registers contain status information associated with an error condition. Some nodes may not preserve this information for all error types. Therefore, field valid bits are used to indicate which fields contain data.
Table 7-10 TLFADRn Register Bit Definitions (Continued) Name Bit(s) Type Function ADRV <24> W1C, 0 Address Valid. Set when contains a valid address from a bus transaction. FBANK <23:20> R, U Failing Bank Number. The bank number field from the command that resulted in an error. This field is Undefined when is zero. RSVD <19> R0 Reserved. Reads as zero. FCMD <18:16> R, U Failing Command Code. The command code field from the command that resulted in an error.
TLESRn—Error Syndrome Registers BB + 0680 through 0740 R/W Address Access The TLESRn registers contain the status information on a data error within a 64-bit slice of the data. TLESR0 contains the error syndrome and status derived from TLSB_D<63:0>, TLSB_ECC<7:0>, and TLSB_DATA_VALID<0>. TLESR1 contains the error syndrome and status derived from TLSB_D<127:64>, TLSB_ECC<15:8>, and TLSB_DATA_VALID<1>.
Table 7-11 TLESRn Register Bit Definitions (Continued) Name Bit(s) Type Function CPU1 <23> RO, 0 CPU 1. When set together with , indicates that CPU1 was involved with sourcing the data error. This bit is Unpredictable when is clear and also when CRECC, CWECC, and UCE are zero. RSVD R0 Memory: Reserved. Reads as zero. RSVD R0 I/O: Reserved. Reads as zero. RO, 0 CPU 0. When set together with , indicates that CPU0 was involved with sourcing the data error.
Table 7-11 TLESRn Register Bit Definitions (Continued) Name Bit(s) Type Function TDE <16> W1C, 0 Transmitter During Error. A status bit set when data transmitted by a node results in error. This bit is Undefined when , , and are zero. SYND1 <15:8> R, U Syndrome 1. Latched error syndrome from second data cycle. This field is Undefined when , , and are zero. SYND0 <7:0> R, U Syndrome 0. Latched error syndrome from first data cycle.
Four error bits in the TLBER register will set as a result of the five error bits in this register.
TLILIDn—Interrupt Level IDENT Registers BB + 0A00 through 0AC0 R/W Address Access Each of the four TLILIDn registers is the topmost (oldest) entry in a queue of the interrupts for that IPL. A read from this register sends the "oldest" interrupt IDENT to the CPU that requests it. When all active interrupts have been read, the TLILIDn register returns zeros. This forces a passive release at the processor.
TLCPUMASK—CPU Interrupt Mask Register BB + 0B00 R/W Address Access The TLCPUMASK register is used to determine which CPUs are to service interrupts. The contents of this register is combined with the interrupt level to form the data to be written to the TLI/OINTRn register. The TLCPUMASK register is loaded at system initialization time (before I/O interrupts are enabled). This register must not be changed while I/O interrupts are enabled.
TLMBPR—Mailbox Pointer Registers BB + 0C00 W Address Access The TLMBPR register posts mailbox requests in an I/O port for access to a CSR on an external I/O bus. Software access to this register is through the single address BB+0C00. CPU hardware selects one of the 16 registers by asserting the value of the CPU’s virtual ID on TLSB_BANK_NUM<3:0>.
Figure 7-1 Mailbox Data Structure 63 QW 0 56 MBZ 48 47 55 HOSE 40 39 MBZ 32 31 30 29 MASK W B QW 1 RBADR <63:0> QW 2 WDATA <63:0> QW 3 UNPREDICTABLE QW 4 RDATA <63:0> QW 5 STATUS QW 6 UNPREDICTABLE QW 7 UNPREDICTABLE 2 1 0 E R R D O N CMD BXB-0174 C-94 Table 7-15 gives the description of the mailbox data structure fields. Table 7-15 Mailbox Data Structure Description QW Bit(s) Name Description 0 <29:0> CMD Remote Bus Command.
Table 7-15 Mailbox Data Structure Description (Continued) QW Bit(s) Name Description 4 <63:0> RDATA Read Data. For read commands, contains the data returned. For write data commands, the field is Unpredictable. 5 <0> DON Done. For read commands, indicates that the , , and fields are valid. For all commands, indicates that the mailbox structure may be safely modified by host software. <1> ERR Error. If set on a read command, indicates that an error was encountered.
TLIPINTR—Interprocessor Interrupt Register BSB + 0040 W Address Access The TLIPINTR register is used by CPU nodes to signal interprocessor interrupts. 31 16 15 RSVD 0 MASK BXB-0497-93 Table 7-16 TLIPINTR Register Bit Definitions Name Bit(s) Type Function RSVD <31:16> W, 0 Reserved. Must be zero. MASK <15:0> W1S, 0 Interprocessor Interrupt Mask. When a given bit is set, an interprocessor interrupt is posted to the corresponding CPU.
TLIOINTRn—I/O Interrupt Registers BSB + 0100 through 0200 W Address Access The TLIOINTRn registers are used by the I/O nodes to signal interrupts from the TLSB I/O system to processors. 20 19 18 17 16 15 31 RSVD 0 VID_MASK IPL 14 INTR IPL 15 INTR IPL 16 INTR IPL 17 INTR BXB-0498-93 Table 7-17 TLI/OINTR Register Bit Definitions Name Bit(s) Type Function RSVD <31:20> R/W, 0 Reserved. Must be zero. INTL <19:16> W1S, 0 Interrupt Level.
means that all CPUs accept writes to these registers. Multiple writes to a register post multiple interrupts. Reads to these locations produce Unpredictable results. A CPU receiving one of the four bits set in its target assignment is expected to respond by reading a TLILIDn register in the I/O node and dispatch an interrupt based on the IDENT vector.
TLWSDQR4-8—Window Space Decr Queue Counter Registers BSB + 0400 through 0500 R/W Address Access The TLWSDQRn registers are used by an I/O node to inform CPU nodes when a window space address register becomes available. One register is assigned to each I/O node by physical node ID (for example, TLWSDQR5 to node 5). If the I/O node acknowledges the CSR write command, it must cycle the data bus and provide data with good ECC. The data is considered Unpredictable and is not used by the receiver.
TLRMDQRX—Memory Channel Decr Queue Counter Register X BSB + 0600 R/W Address Access The TLRMDQR register X is used by an I/O node to inform all nodes when a Memory Channel address register becomes available. One I/O port in physical nodes 4 through 7 that is enabled to handle Memory Channel transactions issues writes to this register. If the I/O node acknowledges the CSR write command, it must cycle the data bus and provide data with good ECC.
TLRMDQR8—Memory Channel Decr Queue Counter Register 8 BSB + 0640 R/W Address Access The TLRMDQR register 8 is used by an I/O node to inform all nodes when a Memory Channel address register becomes available. An I/O port in physical node 8 issues writes to this register. If the I/O node acknowledges the CSR write command, it must cycle the data bus and provide data with good ECC. The data is considered Unpredictable and is not used by the receiver.
TLRDRD—CSR Read Data Return Data Register BSB + 0800 W Address Access The TLRDRD register is used by I/O nodes to return data read from a remote CSR window space read command and complete the remote CSR read command. The CPU virtual ID is asserted on the TLSB_BANK_NUM<3:0> signals when this command is issued. The CPU virtual ID came from the CPU during the CSR window space read command.
TLRDRE—CSR Read Data Return Error Register BSB + 0840 W Address Access The TLRDRE register is used by I/O nodes to signal an error during a remote CSR window space read command and complete the remote CSR read command. The data returned is Unpredictable. The CPU virtual ID is asserted on the TLSB_BANK_NUM<3:0> signals when this command is issued. The CPU virtual ID came from the CPU during the CSR window space read command.
TLMCR—Memory Control Register BSB + 1880 W Address Access The TLMCR register is used by memory nodes to set DRAM timing rates. DRAM timing is dependent on bus cycle time and must be written into each memory node to ensure the most efficient memory operation. DRAM timing affects the memory’s refresh rate. To allow memory nodes to refresh simultaneously, this register sets DRAM timing in all memory nodes in the system.
7.4 CPU Module Registers CPU module registers are divided into four groups: • Module-specific registers • CPU0-specific registers • CPU1-specific registers • Gbus registers The first three groups of registers are implemented in TLSB node space for visibility. Gbus registers reside in the node private space. NOTE: Accesses by a CPU to its own Gbus registers are treated as private accesses and are performed through the TLPRIVATE location in broadcast space (BSB + 0000).
Table 7-20 CPU Module Registers Mnemonic Name Address Diagnostic Setup Register DTag Data Register DTag Status Register CPU Module Configuration Register Console Communications Register 0 for CPU0 DIGA Communications Test Register 0 for DIGA1 DIGA Communications Test Register 0 for DIGA2 DIGA Communications Test Register 0 for DIGA3 Console Communications Register 0 for CPU1 DIGA Communications Test Register 1 for DIGA1 DIGA Communications Test Register 1 for DIGA2 DIGA Communications Test Register 1 for
Table 7-20 CPU Module Registers (Continued) Mnemonic Name Address Memory Channel Range Register for channel 0 Memory Channel Range Register for channel 0 Memory Channel Range Register for channel 1 Memory Channel Range Register for channel 1 BB+1E00 BB+1E40 BB+1E80 BB+1EC0 Interrupt Mask Register for CPU0 Interrupt Mask Register for CPU1 Interrupt Source Register for CPU0 Interrupt Source Register for CPU1 BB+1100 BB+1140 BB+1180 BB+11C0 Module Registers RM_RANGE_0A RM_RANGE_0B RM_RANGE_1A RM_RANGE_1
TLDIAG—Diagnostic Setup Register BB + 1000 R/W Address Access The TLDIAG register is used to configure the module for the various diagnostic modes required for a complete module-level selftest. Only one diagnostic setup register is specified, shared between the two CPUs.
Table 7-22 TLDIAG Register Bit Definitions (Continued) Name Bit(s) Type Function ASRT_FLT <13> R/W, 0 Assert Fault. When set, clearing causes TLSB_FAULT to be asserted to the bus. On power-up reset, this bit is clear, as TLSB_FAULT should not be asserted. On node reset, self-test code sets to force TLSB_FAULT assertion when is cleared. RSVD <12> R/W, 0 Reserved. Must be written as zeros. FDE<3:0> <11:8> R/W, 0 Force Data Error. One bit assigned for each quadword.
Table 7-22 TLDIAG Register Bit Definitions (Continued) Name Bit(s) Type Function DTWR <1> W, 0 DTag Write. When set, causes the DTag entry at the index specified by the next memory space read to be written with the value in the TLDTAGDATA and TLDTAGSTAT registers. The entry is written to the CPU specified by . Valid only when is set. FRIGN <0> R/W, 1 Force Ignore. When set, causes all TLSB transactions to be ignored and disallows transactions from this module to go to the TLSB.
TLDTAGDATA—DTag Data Register BB + 1040 R/W Address Access Diagnostics test the DTag RAMs by writing a value to the DTag and reading the value back to check that the two match. On diagnostic DTag writes, the TLDTAGDATA register is used to set up the DTag data to be written. On diagnostic DTag reads, the TLDTAGDATA register is used to report the DTag data read from the DTag. The TLDTAGDATA register also covers the DTag Data Parity bit.
TLDTAGSTAT—DTag Status Register BB + 1080 R/W Address Access Diagnostics test the DTag status RAMs by writing a value to and reading the value back to check that the two match. On diagnostic DTag writes, the TLDTAGSTAT register is used to set up the value to be written. On diagnostic DTag reads, the TLDTAGSTAT register is used to report the value read from the DTag. This register also has a DTag Status Parity bit.
TLMODCONFIG—CPU Module Configuration Register BB + 10C0 R/W Address Access The TLMODCONFIG register is set by console code to show the module configuration. 31 19 18 17 16 15 14 13 12 RSVD 11 10 9 8 7 6 5 4 3 2 1 0 1 FAULT_DIS CPU_PIPE_DIS SYS_PIPE_DIS BQ_MAX_ENT CQ_MAX_ENT BCIDLETIM: BC Idle Time RM_SIZE LOCKOUT_EN BCACHE_SIZE CPU1_DIS CPU0_DIS BXB-0785-93 Table 7-25 TLMODCONFIG Register Bit Definitions Name Bit(s) Type Function RSVD <31:20> R/W, 0 Reserved.
Table 7-25 TLMODCONFIG Register Bit Definitions (Continued) Name Bit(s) Type Function BQ_MAX_ENT <15:13> R/W, 4 Bus Queue Maximum Entries. Indicates the maximum number of bus queue entries supported. Not all values are supported. CQ_MAX_ENT <12:10> R/W, 4 Cache Queue Maximum Entries. Indicates the maximum number of cache queue entries supported. Not all values are supported. BCIDLETIM <9:6> R/W, F B-Cache Idle Time. Time that BC_IDLE must be asserted before fill data can be returned.
TLEPAERR— ADG Error Register BB + 1500 R/W Address Access The ADG Error Register contains CPU module error bits. These bits are set as a result of errors detected in the ADG.
Table 7-26 TLEPAERR Register Bit Definitions Name Bit(s) Type Function RSVD <31:18> R/W, 0 Reserved. Must be written as zeros. NO_ACK <17:16> W1C, 0 No Acknowledgment. No acknowledgment from one of the DECchip 21164 processors. Bit <16> applies to CPU0; bit <17> to CPU1. CSR_WR_NXM <15> R, 0 CSR Write Not Transmitted. CSR write to other than the TLMBPR register was not acknowledged. WSPC_RD_PEND <14:13> R, 0 Window Space Read Pending.
Table 7-26 TLEPAERR Register Bit Definitions (Continued) Name Bit(s) Type Function M2AAPE1 <3> W1C, 0 MMG to ADG Address Parity Error #1. Set when the ADG detects a parity error on the address bus between CPU1 MMG and the ADG. A parity check is performed after the ADG has assembled the CPU address and cmd/addr parity, as piped from the MMG, and combined it with the CPU command sent directly from the CPU.
TLEPDERR—DIGA Error Register BB + 1540 R/W Address Access The TLEPDERR register contains CPU module error bits. These bits are set as a result of errors detected in the MMG or any of the DIGA chips. This register resides in DIGA0.
Table 7-27 TLEPDERR Register Bit Definitions Name Bit(s) Type Function RSVD <31:3> R/W, 0 Reserved. Must be written as zeros. GBTO <2> W1C, 0 Gbus Timeout Error. Set when DIGA0 issues a Gbus read and fails to receive Gbus Acknowledge within the Gbus timeout period. This error indicates that the CPU module is unable to access some Gbus resource. This error also results in a TLSB data timeout error and causes assertion of TLSB_FAULT (unless is asserted).
TLEPMERR—MMG Error Register BB + 1580 R/W Address Access The TLEPMERR register contains CPU module error bits. These bits are set as a result of errors detected in the MMG. This register also contains the node reset status bit.
Table 7-28 TLEPMERR Register Bit Definitions Name Bit(s) Type Function RSVD <31:7> R/W, 0 Reserved. Must be written as zeros. RSTSTAT <6> W1C, 0 Node Reset Status. When set, indicates that the node was reset by writing 1 to TLCNR. D2DCPE3 <5> W1C, 0 DIGA to DIGA CSR Parity Error #3. Set when DIGA3 detects a parity error on the DIGA to DIGA CSR bus. This error can occur when a CSR in DIGA3 is being written or read.
Table 7-28 TLEPMERR Register Bit Definitions (Continued) Name Bit(s) Type Function D2MCPE <2> W1C, 0 DIGA to MMG CSR Parity Error. Set when the MMG detects a parity error on the DIGA to DIGA CSR bus. This error can occur when a CSR in the MMG is being written or read. This error can be detected on either CSR data or CSR command/address information, but only when MMG’s DCSR valid bit is asserted, or during a DIGA0 to MMG data movement. This error indicates that CSR data has been corrupted.
TLEP_VMG—Voltage Margining Register BB + 15C0 R/W Address Access The TLEP_VMG register is implemented in DIGA1. It drives the voltage margining circuit on the CPU module to vary the 5 V and 3.3 V supplies. The otherwise unused (on DIGA1) interrupt lines are used for this function. Any value written into this register is cleared on reset.
TLINTRMASK0–1—Interrupt Mask Registers BB + 1100, BB + 1140 R/W Address Access The TLINTRMASK0–1 registers are used to enable interrupts to the CPUs. TLINTRMASK0 controls interrupts on CPU0 and TLINTRMASK1 on CPU1.
Table 7-30 TLEPDERR Register Bit Definitions Name Bit(s) Type Function RSVD <31:9> R/W, 0 Reserved. Must be written as zeros. Ctrl/P_HALT_ENA <8> R/W, 0 Ctrl/P Halt Enable. Enables halt through ^P if of GBUS$MISCR is not set, and if a ^P Halt interrupt is received from the Gbus. HALT_ENA <7> R/W, 0 CPU Halt Enable. Enables halts by writes to TLCNR for this CPU. INTIM_ENA <6> R/W, 0 Interval Timer Interrupt Enable.
TLINTRSUM0–1—Interrupt Source Registers BB + 1180, BB + 11C0 R/W Address Access The DECchip 21164 has seven interrupt lines. They are as follows: 1. 2. 3. 4. IRQ<3:0> - Interrupt request lines mapping to IPL17:IPL14 SYS_MCH_CHK_IRQ - Machine check interrupt request MCH_HLT_IRQ - Machine halt interrupt request PWR_FAIL_IRQ - Power fail interrupt request Multiple interrupts from different devices may be targeted at the same interrupt request pin of the CPU.
Table 7-31 TLINTRSUM Register Bit Definitions Name Bit(s) Type Function RSVD <31:29> R/W, 0 Reserved. Must be written as zeros. HALT <28> R, 0 Halt. CPU halt was written in TLCNR (this CPU) and TLINTR is set. Ctrl/P_HALT <27> W1C, 0 Ctrl/P Halt. Ctrl/P_HALT has been received for this CPU. Cleared with a write of 1. IPL17_INTR <26:22> R, 0 IPL17 Interrupts. Indicator of outstanding interrupts at IPL17.
Table 7-31 TLINTRSUM Register Bit Definitions (Continued) Name Bit(s) Type Function IPL14_INTR <11:7> R, 0 IPL14 Interrupts. Indicator of outstanding interrupts at IPL14. If a bit is set in this field, it indicates that there is at least one interrupt outstanding at IPL17 from the node number associated with the bit. IPL14_INTR Bit Node Number <11> <10> <9> <8> <7> 8 7 6 5 4 INTIM_INTR <6> W1C, 0 Interval Timer Interrupt. The interval timer can be set to interrupt or to be polled.
TLCON00,01,10,11—Console Communications Regs BB + 1200 & 1400; BB + 1300 & 1440 R/W Address Access Two 32-bit wide register scratch pads are provided for each CPU on a module for communications between CPUs. Bits in these two registers are not allocated to any particular function and are under software control. These registers could be used to provide a lock mechanism for access to module-level devices, to pass diagnostic information, arbitration for module control, and so on.
TLCON0A,0B,0C,1A,1B,1C—DIGA Comm. Test Regs BB + 1240, 1280, & 12C0; BB + 1340, 1380, & 13C0 R Address Access DIGA Communications Test registers are used by diagnostic selftest code only. 31 0 DIGA Communications Test Reg 0 DIGA Communications Test Reg 1 BXB-0724-94 The Console Communications registers are implemented in DIGA0. The same registers exist in DIGA1,2,3. To facilitate individual loads of DIGA1,2,3, the Console Communications registers are used as scratchpad areas.
RM_RANGE_nA,B—Memory Channel Range Regs BB + 1E00 through 1EC0 R/W Address Access The Memory Channel Range registers define the two separate memory ranges to be set up on the CPU module.
Table 7-32 Memory Channel Range Register Bit Definitions Name Bit(s) Type Function VALID <31> R/W, 0 Valid. When set, the contents of this register are valid. RSVD <30:27> R/W, 0 Reserved. Read as zeros. BASE_ADR<38:20> <26:8> R/W, 0 Base Address <38:20>. The address of Memory Channel region. Aligned to the extent size. RSVD <7:5> R/W, 0 Reserved. Read as zeros. INTLV_EN <4> R/W, 0 RM Interleave Enable.
TLDMCMD—Data Mover Command Register BB + 1600 R/W Address Access The TLDMCMD register controls the data mover transactions.
Table 7-33 TLDMCMD Register Bit Definitions Name Bit(s) Type Function DM_DONE <31> W1C, 0 Data Movement Done. When set, indicates that the required function has been completed and that the data mover is idle. This bit clears when the CPU that initiated the data mover transaction writes one to it. Note that when this bit is set, only the CPU identified in TLDMCMD can change any value in this register. Reads of this bit by other than the CPU identified in return zero.
Table 7-33 TLDMCMD Register Bit Definitions (Continued) Name Bit(s) Type Function DM_CMD <9:8> R/W, 0 Data Mover Command. Encodes the data mover command. Encoding 00 Initialize memory at the addresses specified by the TLDMADRA register and the data length field to zero. 01 Read blocks from addresses specified by the TLDMADRA register and the data length field. The read causes the blocks to become shared.
TLDMADRA—Data Mover Source Address Register BB + 1680 W Address Access The TLMADRA register contains the source address of the data mover transaction. 31 30 29 0 SRC_ADR <38:9> BXB-0772-93 RSVD Table 7-34 TLDMADRA Register Bit Definitions Name Bit(s) Type Function RSVD <31:30> W, 0 Reserved. Must be written as zeros. SRC_ADR<38:9> <29:0> W, 0 Source Address Bits <38:9>. Bit <39> is implied zero. Block moves are always aligned on 512-byte boundaries. Hence bits <8:0> are also implied zero.
TLDMADRB—Data Mover Destination Address Reg BB + 16C0 W Address Access The TLMADRB register contains the destination address of the data mover transaction. 31 30 29 0 DEST_ADR <38:9> BXB-0771-93 RSVD Table 7-35 TLDMADRB Register Bit Definitions Name Bit(s) Type Function RSVD <31:30> R/W, 0 Reserved. Must be written as zeros. DEST_ADR<38:9> <29:0> R/W, 0 Destination Address Bits <38:9>. Bit <39> is implied zero. Block moves are always aligned on 512-byte boundaries.
GBUS$WHAMI Address Access FF C000 0000 R/W The GBUS$WHAMI register provides node ID, CPU number, and reflects the status of some backplane signals. 7 6 5 4 3 1 0 0 MFG_MODE_L TLSB_CONWIN TLSB _BAD CPU_NUM NID BXB-0514-93 Table 7-36 GBUS$WHAMI Register Bit Definitions Name Bit(s) Type Function RSVD <7> R0 Reserved. Reads as zero. MFG_MODE_L <6> R Manufacturing Mode Low. Tied to a centerplane signal. Used by manufacturing to indicate that the module is in a manufacturing environment.
GBUS$LED0,1,2 Address Access FF C100 0000, FF C200 0000, FF C300 0000 R/W The GBUS$LEDn registers are used by diagnostics to indicate test numbers for both CPUs. LEDs are illuminated by writing a one to the appropriate bits in one of the GBUS$LEDn registers. GBUS$LED0 is for CPU0 and drives a 7-segment display. GBUS$LED1 is for CPU1 and drives a 7-segment display. GBUS$LED2 is a general purpose display of eight individual registers.
GBUS$MISCR Address Access FF C400 0000 R The GBUS$MISCR register is used to gather various read bits that show module configuration.
Table 7-37 GBUS$MISCR Register Bit Definitions Name Bit(s) Type Function CONWIN1R <7> R, 0 Console Winner CPU1 Read. When set, indicates that CPU1 is running console. This is a read copy of the write-only bit implemented in GBUS$MISCW. CONWIN0R <6> R, 0 Console Winner CPU0 Read. When set, indicates that CPU0 is running console. This is a read copy of the write-only bit implemented in GBUS$MISCW. RSVD <5> R0 Reserved. Reads as zero. TLSB_RUN <4> R, 0 TLSB Run.
GBUS$MISCW Address Access FF C500 0000 W The GBUS$MISCW register is used to gather write bits that control various functions. 7 6 5 4 3 CONWIN1R CONWIN0R RSVD TLSB_RUN 2 1 0 CACSIZ: B-Cache Size DRIVE_BAD TLSB_SECURE BXB-0515-93 Table 7-38 GBUS$MISCW Register Bit Definitions Name Bit(s) Type Function CONWIN1W <7> W, 0 Console Winner CPU1 Write. This bit is set to indicate that CPU1 has won console arbitration. CONWIN0W <6> W, 0 Console Winner CPU0 Write.
GBUS$TLSBRST Address Access FF C600 0000 R/W The GBUS$TLSBRST register is used to initiate a system reset sequence. When this register is loaded with any value, the CCL RESET signal is asserted by the CPU module for 128 TLSB cycles. The CCL then drives TLSB_RESET for 16 µs. No register is implemented.
GBUS$SERNUM Address Access FF C700 0000 R/W The GBUS$SERNUM register is used to read and write an SROM on the clock module where the system serial number is stored. All reads and writes to this register are done by software. 7 6 5 4 3 STP PIUA PIUB EXPSEL 2 1 0 SROM_CLK RCV_DATA XMT_DATA BXB-0728-93 Table 7-39 GBUS$SERNUM Register Bit Definitions Name Bit(s) Type Function STP <7> R/W, 0 Self-Test Passed. Drives large green STP LED on the CPU module. PIUA <6> R, 0 PIUA Status.
Table 7-39 GBUS$SERNUM Register Bit Definitions (Continued) Name Bit(s) Type Function EXPSEL <4:3> R/W, 0 Expander Select. Selects which cabinet the power supply UART lines are logically connected to and, therefore, which set of three 48V power supplies are connected to the PS lines. May be used by console when TLDIAG is set for communication between the CPUs. EXPSEL Selection 00 PS lines talk to the main CPU cabinet. 01 PS lines talk to the right expander cabinet.
7.5 Memory-Specific Registers Table 7-40 lists the memory-specific registers. Descriptions follow. Refer to Table 7-2 for the TLSB registers implemented on the memory module.
SECR—Serial EEPROM Control/Data Register BB + 0000 1800 R/W Address Access The SECR register is used to access the EEPROM on the memory module. Access to the EEPROM is accomplished by continual updates of this register by software. 31 4 3 2 1 0 RSVD SCLK XMT_SDAT RCV_SDAT BXB-0729-94 Table 7-41 SECR Register Bit Definitions Name Bit(s) Type Function RSVD <31:3> R0 Reserved. Read as zero. SCLK <2> R/W, 0 Serial Clock. Used to implement the EEPROM serial clock interface by software.
MIR—Memory Interleave Register BB + 0000 1840 R/W Address Access The MIR register is used by memory to determine DRAM RAS selection based upon how a given memory module is configured on the TLSB. Console software initializes this register upon start-up after system or node reset.
Table 7-42 MIR Register Bit Definitions Name Bit(s) Type Function VALID <31> R/W, 0 Valid. When set, enables the module to respond to TLSB memory space transactions. RSVD <30:3> R0 Reserved. Read as zero. INTLV <2:0> R/W, 0 Interleave. The value of this field loaded by console during system initialization determines whether this module is 1,2,4,8 or 16-way interleaved in the system.
MCR—Memory Configuration Register Address Access BB + 0000 1880; BSB + 0000 1880 R/W The MCR register provides information about the DRAM array structure including DRAM type and number of strings installed. It includes a battery OK indication and battery disable when used with the SRAM option. This information is required by the console to set up the eight address mapping registers in each TLSB commander node and the MIR register located on each memory module.
Table 7-43 MCR Register Bit Definitions Name Bit(s) Type Function BAT <31> R, none1 Battery OK. Indicates the state of the batteries when memory is configured to support the SRAM (NVRAM) option. When set, the battery supply is sufficient and present. When clear, two possibilities exist. First, if the battery has been disconnected through bit <30>, a zero will indicate that the battery disable circuitry is functioning properly.
Table 7-43 MCR Register Bit Definitions (Continued) Name Bit(s) Type Function OPTION <9> R, X1 Option Installed. This field specifies whether the SRAM option or the DRAM option is installed. When read as a value of zero, the SRAM is installed. The SRAM option is used to support NVRAM (nonvolatile memory). When this mode is selected, refresh and self-test are inhibited from being executed. Option Memory Option 0 1 70 ns SRAMs 60 ns DRAMs (default) SHRD <8> R/W, 0 Shared.
Table 7-43 MCR Register Bit Definitions (Continued) Name Bit(s) Type Function DTR <5:4> R/W, 0 DRAM Timing Rate. This field is used to modify the DRAM timing and refresh rate. At reset, DRAM timing defaults to supporting a 10 ns bus cycle time, while the refresh rate defaults to supporting a 30 ns bus. is normally written by console through a TLSB broadcast write command. This ensures that all memories will remain syncronized as to when they refresh the DRAMs.
STAIR—Self-Test Address Isolation Register BB + 0000 18C0 R/W Address Access The STAIR register is used to isolate self-test failures to a given address segment or segments in the case of multiple failures in a module. This register breaks up a memory module into at most 32 distinct address segments, which would be the case of a 2-Gbyte module. Each segment maps 64 Mbytes (1 meg 64-byte blocks) of memory independent of the selected DRAM (4 Mbit, 16 Mbit).
Table 7-45 STAIR Register Bit Correspondence of Memory Address Segments Bit Set Failing Address Range Bit Set Failing Address Range 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0000 0000 – 03FF FFFF 0400 0000 – 07FF FFFF 0800 0000 – 0BFF FFFF 0C00 0000 – 0FFF FFFF 1000 0000 – 13FF FFFF 1400 0000 – 17FF FFFF 1800 0000 – 1BFF FFFF 1C00 0000 – 1FFF FFFF 2000 0000 – 23FF FFFF 2400 0000 – 27FF FFFF 2800 0000 – 2BFF FFFF 2C00 0000 – 2FFF FFFF 3000 0000 – 33FF FFFF 3400 0000 – 37FF FFFF 3800 0000 – 3BFF FFFF 3C00 00
STER—Self-Test Error Register BB + 0000 1900 R/W Address Access The STER register contains address information pertaining to data mismatch failures while self-test executes in POEM (pause on error) mode. The contents of this register when read after an error has been detected in POEM mode can be used to isolate the failing DRAM string and to indicate which of the four MDIs the error was detected in.
Table 7-46 STER Register Bit Definitions Name Bit(s) Type Function RSVD <31:8> R0 Reserved. Read as zero. STE3 <7> W1C, 0 Self-Test Error in MDI3. Set during POEM mode when MDI3 detects a data mismatch error. The setting of this bit locks bit <6> (STE2), bit <5> (STE1), bit <4> (STE0), and bits <2:0> (FSTR) of the failing string field1. STE2 <6> W1C, 0 Self-Test Error in MDI2. Set during POEM mode when MDI2 detects a data mismatch error.
MER—Memory Error Register BB + 0000 1940 R/W Address Access The MER register provides the DRAM string that failed when an ECC error is detected during a memory read transaction. This information in conjunction with the error syndrome registers can be used to isolate correctable ECC errors down to a failing DRAM component. This information is logged by the OS error logging software and written to the serial EEPROM.
MDRA—Memory Diagnostic Register A BB + 0000 1980 R/W Address Access MDRA register A is used by diagnostics and manufacturing to force error conditions in the memory module and isolate failures.
Table 7-48 MDRA Register Bit Definitions (Continued) Name Bit(s) Type Function RFR <29:28> R/W, 01 Refresh Rate. Determines the refresh rate of the module. Refresh Rate 00 01 10 11 1X 2X (Default) 4X Reserved RSVD <27:9> R0 Reserved. Read as zero. DEDA <8> R/W, 01 TLSB_DATA_ERROR Disable. When set and used in conjunction with POEM or FRUN modes, TLSB_DATA_ERROR will not assert if an error is detected.
Table 7-48 MDRA Register Bit Definitions (Continued) Name Bit(s) Type Function POEM1 <6> R/W, 01 Pause on Error Mode. When set, self-test will halt execution upon the detection of a data mismatch error. TLSB_DATA_ERROR is asserted and remains asserted providing that is cleared, until either is set or the module is reset. This bit is used in conjunction with to execute self-test in this mode.
Table 7-48 MDRA Register Bit Definitions (Continued) Name Bit(s) Type Function FCAPE <2> R/W, 0 Force Column Address Parity Error. When set, incorrect DRAM column address parity is written into the addressed location when a match is detected between the TLSB address and the MDRB register and when is also set. FRAPE <1> R/W, 0 Force Row Address Parity Error.
MDRB—Memory Diagnostic Register B BB + 0000 19C0 R/W Address Access Memory Diagnostic Register B contains a 32-bit 64-byte aligned address value that is directly compared to TLSB_ADR<37:6>, or an address generated by the self-test address generator. The value loaded into this register is used in conjunction with MDRA and DDR0:3 to cause a specific data bit and/or check bit to be flipped whenever a TLSB memory write address matches the value contained in this register.
STDERA,B,C,D,E—Self-Test Data Error Registers Address Access BB + 0001 0000 to 0001 C100 R/W The four sets of STDERx_n registers are used to isolate self-test failures down to a single failing bit or bits. When self-test is executed any data bit error(s) that are detected by the self-test data compare logic will set the appropriate data bit(s) in these registers. The operation and contents of this register can be affected by bits <2:0> of the DDR0:3 registers in the MDI ASICs.
Table 7-50 STDER A, B, C, D Register Bit Definitions Name Bit(s) Type Function STDERA <31:0> R/W, 0 Self-Test Data Error Register_A. One or more bits set indicate a self-test data bit error. The contents of this register can be used to isolate self-test failures to a single failing bit. This register can be read or written as an aid in determining proper CSR operation. STDERB <31:0> R, 0 Self-Test Data Error Register_B. One or more bits set indicate a self-test data bit error.
Table 7-51 STDERE Register Bit Definitions Name Bit(s) Type Function RSVD <31:19> R0 Reserved. Read as zero. VRC <18:16> R, X Valid Residue Check. This 3-bit read-only field is loaded at the beginning of the third pass in self-test and specifies which one of eight values will be used by the self-test data-checking logic to determine that the self-test data linear feedback shift register logic is working correctly.
DDR0:3—Data Diagnostic Registers BB + 0001 0140; 0001 04140; 0001 8140; 0001 C140 R/W Address Access There are four DDR registers, one in each of the four MDI ASICs. They are used by diagnostics and manufacturing to force error conditions, to isolate failures, and to margin the DC to DC power converters.
Table 7-52 DDRn Register Bit Definitions (Continued) Name Bit(s) Type Function EFLPD <15> R/W, 0 Enable Flip Data Bit. When set in conjunction with MDRA, the data bit selected in DFLP<13:8> is flipped during memory write transactions. This function allows diagnostics to check ECC error detection logic. NOTE: Setting both EFLPD and EFLPC results in Uncorrectable ECC written into memory. EFLPC <14> R/W, 0 Enable Flip ECC Check Bit.
Table 7-52 DDRn Register Bit Definitions (Continued) Name Bit(s) Type Function ICFR <2> R/W, 0 Inhibit Clear on Free Run. When set in conjunction with MDRA, the contents of the STDER registers accumulate errors detected by self-test. When ICFR is cleared, the contents of the STDER registers will be cleared when selftest reenters the start execution phase due to set. This bit is valid only when selftest is in free run mode. If set during other selftest modes, operation is Undefined.
7.6 I/O Port-Specific Registers The I/O port responds to all addresses within its node space. If, however, the I/O port receives a read to a nonimplemented CSR, the I/O port returns Unpredictable data, with good ECC. Table 7-53 shows the mapping of the I/O port-specific registers.
RMRR0-1—Memory Channel Range Registers BB + 1E00 to 1EC0 R/W Address Access The I/O port houses two incoming Memory Channel address range register pairs. These register pairs are not specific to a single hose, but are generic across all four hoses. The I/O port compares the addresses of all incoming DMA write packets to the contents of these registers, regardless of the originating Up Hose. One pair (RMRR0n) checks for matches of incoming DMA addresses targeted to an I/O port in TLSB node 8.
Table 7-54 RMRR0-1 Register Bit Definitions Name Bit(s) Type Function VALID <31> R/W, 0 Valid. When set, the contents of this register is valid. RSVD <30:28> R/W, 0 Reserved. Read as zeros. BASE_ADR<38:20> <27:8> R/W, 0 Base Address <39:20>. The address of Memory Channel region. Aligned to the extent size. RSVD <7:5> R/W, 0 Reserved. Read as zeros. INTLV_EN <4> 0 Memory Channel Interleave Enable. Always set to zero. Memory Channel interleave is never enabled.
ICCMSR—I/O Control Chip Mode Select Register BB + 2000 R/W Address Access The ICCMSR register can be used by software to select the desired mode of operation for the I/O port. 31 4 3 2 1 0 RSVD SUP_CTL<1:0> ARB_CTL<1:0> BXB-0768-94 Table 7-55 ICCMSR Register Bit Definitions Name Bit(s) Type Function RSVD <31:4> R/W, 0 Reserved. Must be zero.
Table 7-55 ICCMSR Register Bit Definitions (Continued) Name Bit(s) Type Function SUP_CTL<1:0> <3:2> R/W, 0 Suppress Control. This field can be programmed to select the number of outstanding transactions the I/O port will permit on the TLSB before it asserts TLSB_ARB_SUP. No node, including the I/O port, may arbitrate for the TLSB address bus until TLSB_ARB_SUP is deasserted. The field is defined as follows: SUP_CTL Function 00 Suppress after 16 transactions.
Table 7-55 ICCMSR Register Bit Definitions (Continued) Name Bit(s) Type Function SUP_CTL<1:0> <3:2> R/W, 0 SUP_CTL Function 11 Suppress after 2 transactions. If the I/O port detects 2 outstanding transactions pending on the TLSB, it asserts TLSB_ARB_ SUP during the command/ address cycle of the second transaction for one cycle, then deasserts it for one cycle.
Table 7-55 ICCMSR Register Bit Definitions (Continued) Name Bit(s) Type Function ARB_CTL<1:0> <1:0> R/W, 0 ARB_CTL Function 00 (Cont) If the I/O port does not issue a back-to-back request to the same memory bank, that is, at least one potential request cycle to that memory bank occurs, then the next request to that memory bank by the I/O port can be initiated through TLSB_REQ8_HIGH.
Table 7-55 ICCMSR Register Bit Definitions (Continued) Name Bit(s) Type Function ARB_CTL<1:0> <1:0> R/W, 0 ARB_CTL Function 01 Toggle 50% high/50% low mode. The I/O port always arbitrates on TLSB_REQ8_HIGH once, followed by TLSB_REQ8_LOW once for a given memory bank. This guarantees that the I/O port wins that memory bank at least 50% of the time. It also guarantees that the I/O port cannot lock out a memory bank.
ICCNSE—I/O Control Chip Node-Specific Error Reg BB + 2040 R/W Address Access The ICCNSE register logs the collective error information relative to the internal operations of the I/O port. The following errors leave the I/O port in an Unpredictable state. If any of these errors occur, the I/O port should be reset to initialize it to a predictable state. UP_HDR_IE<1:0> ICR_IE ICR_UP_VRTX_ERR<1:0> DN_VRTX_ERR<1:0> NOTE: Some errors are specific to the IDR0–3 data path gate arrays.
Table 7-56 ICCNSE Register Bit Definitions Name Bit(s) Type Function INTR_NSES <31> R/W, 0 Interrupt on NSES. When set, globally enables all error interrupt sources on the I/O port. If an error is detected and this bit is set, the I/O port posts a level 17 interrupt to the CPU. The subsequent read of TLILID3 returns the vector from the IDR Vector Register (IDPVR). When this bit is clear, no interrupt is posted as the result of an I/O port detected error.
Table 7-56 ICCNSE Register Bit Definitions (Continued) Name Bit(s) Type Function UP_VRTX_ERR <26:25> W1C, 0 Up Vortex Error. This field is a composite error field of possible Up Turbo Vortex errors that the ICR gate array can detect. There are two separate Up Turbo Vortex buses, one for hose<3:2> and one for hose<1:0>.
Table 7-56 ICCNSE Register Bit Definitions (Continued) Name Bit(s) Type Function MULT_INTR_ERR <22> W1C, 0 Multiple Interrupt Error. The I/O port has four TLILID FIFOs, one for each IPL. Each TLILID FIFO is four entries deep, so it can accept up to four pending interrupts for the given IPL level. The MULT_INTR_ERROR bit is set if a TLILID FIFO overflows.
Table 7-56 ICCNSE Register Bit Definitions (Continued) Name Bit(s) Type Function UP_HOSE_PKT_ERR <15:12> W1C, 0 Up Hose Packet Error. This field indicates that one of the Up HDR gate arrays detected either an illegal command or sequence error on the corresponding Up Hose. An IPL17 interrupt is generated when these bits set if interrupts are enabled by INTR_NSES (ICCNSE<31>). UP_HOSE_OFLO <11:8> W1C, 0 Up Hose FIFO Overflow.
ICCDR—I/O Control Chip Diagnostic Register Address Access BB + 2080 R/W The ICCDR register can be programmed by diagnostics to force errors on the TLSB and Turbo Vortex buses for the I/O port to detect. Hose errors can also be forced, but this is a function of the loopback feature. Refer to the TurboLaser I/O port functional specifications for details. System bus errors are transmitted on the TLSB and are detected by the I/O port when the signals are received back.
Table 7-57 ICCDR Register Bit Definitions Name Bit(s) Type Function ENA_DMA_HID <31> R/W, 0 Enable DMA Hose ID. When set and the I/O port is hard-wired to enable debug mode, the number of the hose that originated the transaction is inserted at address bits <26:25> for memory transactions (that is, A<28>=0). This bit is only valid when the I/O port is hard-wired to enable debug mode. Otherwise, the bit has no effect on I/O port operation. RSVD <30:9> R/W, 0 Reserved. Must be zero.
Table 7-57 ICCDR Register Bit Definitions (Continued) Name Bit(s) Type Function DIS_TLSB_FAULT <4> R/W, 0 Disable TLSB Fault. Setting this bit prevents the I/O port from driving TLSB_FAULT even if a system fatal error condition is detected by the I/O port. It allows diagnostics to force various fatal TLSB errors (such as APE, ATCE, BBE, DTO, DSE) and various fatal Up Turbo Vortex errors without crashing the system.
ICCMTR—I/O Control Chip Mailbox Transaction Reg BB + 20C0 R Address Access The ICCMTR register indicates if a mailbox transaction is in progress and the targeted hose of the transaction. This register is physically located in the ICR gate array.
Table 7-58 ICCMTR Register Bit Definitions Name Bit(s) Type Function RSVD <31:4> R0 Reserved. Read as zeros. MBX_TIP<3:0> <3:0> W1C, 0 Mailbox Transaction in Progress. Indicates that the I/O port has transmitted a Mailbox Command packet, targeting the corresponding hose, across one of the Down Turbo Vortex buses. When the corresponding Mailbox Status packet is received and processed, the bit is cleared.
ICCWTR—I/O Control Chip Window Transaction Reg BB + 2100 R Address Access The ICCWTR register indicates if a window transaction is in progress and the targeted hose of the transaction. This register is physically located in the ICR gate array. 31 4 3 0 RSVD WIP<3:0> BXB-0761-94 Table 7-59 ICCWTR Register Bit Definitions Name Bit(s) Type Function RSVD <31:4> R0 Reserved. Read as zeros. WIP<3:0> <3:0> W1C, 0 Window in Progress.
IDPNSE0–3—I/O Data Path Node-Specific Error Regs Address Access BB + 2A40, 2140, 2240, 2340 R/W The IDPNSE0–3 registers are physically located in the corresponding IDR0–3 I/O port gate arrays. They log the collective error information related to the internal operations of the gate arrays. The following errors leave the I/O port in an Unpredictable state. IDR_IE IDR_UP_VRTX_ERR<1:0> If any of these errors occur, the I/O port should be reset to initialize it to a predictable state.
Table 7-60 IDPNSE0–3 Register Bit Definitions Name Bit(s) Type Function HOSEn_RESET <31> W, 0 HOSEn Reset.
Table 7-60 IDPNSE0–3 Register Bit Definitions (Continued) Name Bit(s) Type Function IDR_UP_VRTX_ERR <26:25> W1C, 0 IDR Up Vortex Error.
Table 7-60 IDPNSE0–3 Register Bit Definitions (Continued) Name Bit(s) Type Function HOSEn_PWROK_TR <3> W1C, X HOSEn Power OK Transitioned. This bit is latched whenever the associated HOSEn_ PWROK signal transitions. HOSEn_PWROK can then be read to determine the reason why this bit set. A PWROK transition from 0 to 1 indicates a power-up, while a PWROK transition of 1 to 0 indicates a power-down.
Table 7-60 IDPNSE0–3 Register Bit Definitions (Continued) Name Bit(s) Type Function HOSEn_PWROK <1> R, X HOSEn Power OK. This bit is derived from the HOSEn_PWROK signal and reflects its current level. If the associated hose cable is connected properly to the I/O adapter and has sufficient power to process commands, then this bit will be a 1. The transition of this bit from either 1 to 0 or 0 to 1 causes HOSEN_PWROK_TR<3> to set. This bit has no effect on I/O port interrupts.
IDPDRn—I/O Data Path Diagnostic Registers Address Access BB + 2A80, 2180, 2280, 2380 R/W The IDPDRn registers can be programmed by diagnostics to force errors on the TLSB and Turbo Vortex buses for the I/O port to detect. System bus errors are transmitted on the TLSB and are detected by the I/O port when the signals are received back. These registers can also be used to force errors to be generated across the Down Turbo Vortex buses.
Table 7-61 IDPDR0–3 Register Bit Definitions Name Bit(s) Type Function VOLT_MARG <31> R/W, 0 Voltage Margin. When set, the module’s 5.0 and 3.35 volt DC to DC converters are margined over a +/− 5% range. IDR Register Voltage Margin IDPDR0 IDPDR1 IDPDR2 IDPDR3 5.0 5.0 3.5. 3.5 +5% −5% +5% −5% NOTE: If both plus and minus margining bits are set for a given voltage, the DC to DC converter goes to its nominal output voltage. The VOLT_MARG bit is not cleared by a node reset.
Table 7-61 IDPDR0–3 Register Bit Definitions (Continued) Name Bit(s) Type Function FRC_VAL_SEQ_ERR <19> R/W, 0 Force Down Valid Sequence Error. When set, forces VALID to be asserted for an extra cycle for down Turbo Vortex Mailbox Command packets. FRC_DN_DPE <18> R/W, 0 Force Down Data Parity Error. When set, forces bad parity on the down Turbo Vortex bus as it exits the IDR. This bit can be set independently in each IDR to force bad parity in different longwords.
Table 7-62 Error Matrix for Force Error Bits Set Diagnostic Bit Perform Transaction Detect Error IDPDR0 IDPDR0 IDPDR0 IDPDR0 Write to CSR in IDR1 Write to CSR in IDR2 Write to CSR in IDR3 Write to CSR in ICR IDPNSE1 IDPNSE2 IDPNSE3 ICCNSE IDPDR1 IDPDR2 IDPDR3 Read to CSR in IDR1 Read to CSR in IDR2 Read to CSR in IDR3 I
IDPVR—I/O Data Path Vector Register BB + 2B40 R/W Address Access The IDPVR register is loaded by software with the vector associated with I/O port-specific errors. 31 0 16 15 VECTOR<15:0> RSVD BXB-0759-93 Table 7-63 IDPVR Register Bit Definitions Name Bit(s) Type Function RSVD <31:16> R/W, 0 Reserved. Read as zeros. VECTOR<15:0> <15:0> R/W, 0 Vector<15:0>. Contains the vector that will be returned as read data when the CPU servicing an I/O port error interrupt reads the TLILID3 register.
IDPMSR—I/O Data Path Mode Select Register BB + 2B80 R/W Address Access The IDPMSR register can be used by software to select the desired mode of operation for the I/O port.
Table 7-64 IDPMSR Register Bit Definitions Name Bit(s) Type Function RSVD <31:2> R/W, 0 Reserved. Read as zeros. HDR_LPBCK_EN <1> R/W, 0 HDR Loopback Enable. When set, enables the I/O port to internally loopback Mailbox Command packets and Sparse Window Read packets between the Down Hose and Up Hose. When set, the ICR automatically disables all attached I/O adapter modules by driving the hose error signal (HOS_ERROR) on all Up Hoses.
IBR—Information Base Repair Register BB + 2BC0 R/W Address Access The IBR register is used to access the EEPROM located on the I/O port. To access the EEPROM, software continually updates the IBR register to transfer command, address, and data to and from the device. Writing an alternating one and zero pattern to IBR implements the serial data clock used for the EEPROM protocol.
Table 7-65 IBR Register Bit Definitions Name Bit(s) Type Function RSVD <31:3> R/W, 0 Reserved. Read as zeros. SCLK <2> R/W, 0 Serial Clock. Used to implement the FEPROM serial clock interface by software. When this bit is written with a one, the FEPROM serial clock input is forced to a logic high. When this bit is cleared, the serial clock input is forced to low logic level. XMT_SDAT <1> R/W, 1 Transmit Serial Data.
7.7 KFTIA Specific Registers Registers specific to the integrated I/O module, the KFTIA (registers in addition to those specific to the KFTHA module) can be grouped in two classes: • PCIA registers • PCI device registers The discussion of these registers is beyond the scope of this manual. PCIA registers are discussed in the DWLPA PCI Adapter Technical Manual. PCI device registers are discussed in their respective specifications.
Chapter 8 Interrupts The TLSB supports both vectored and nonvectored interrupts. • Vectored interrupts are the traditional I/O adapter interrupts, where the processor dispatches the interrupt based on an IDENT (identification) vector supplied by the adapter. The value of the IDENT vector is loaded into each adapter at system initialization. • Nonvectored interrupts are those interrupts that have been architecturally defined mechanisms for entering the relevant interrupt service routine.
• At most, four interrupts at levels 0, 1, and 2 can be pending on the TLSB bus (one per interrupt level 14, 15, and 16, respectively, per I/O hose) per I/O node. • However, up to five interrupts at level 3 can be pending on the TLSB bus (one at interrupt level 17 per I/O hose and one internally generated I/O module error interrupt) per I/O node. • When a CPU module performs a CSR read of a given TLILIDn register, the I/O module considers the relevant interrupt to be serviced.
• The targeted CPUs are interrupted at an appropriate level and the CPU issues a CSR read transaction over the TLSB bus to the TLILIDn register for the relevant interrupt level to get the interrupt vector. • After the CSR read of TLILIDn is successfully completed, the I/O module considers the interrupt to be serviced. • If an interrupt targets more than one CPU, the first CPU to win the TLSB for the CSR read of TLILIDn gets the relevant IDENT information.
Refer to Chapter 7 for the format of all registers used in the interrupt operation. 8.3.1.1 Virtual Node Identification - TLVID TLSB system functionality requires that certain units be identified uniquely, independent of physical location in the system. Specifically, individual memory banks and CPUs must be uniquely addressable entities at the system level, independent of their physical node ID.
only to TLIOINTR4. Interrupts at the IPL level(s) specified in bits <19:16> are targeted at the VIDs specified in bits <15:0> (see Chapter 7). 8.3.2 Generating Interrupts The TLCPUMASK for each I/O port and the TLINTRMASK for each CPU are set up by the console. To generate an interrupt, the I/O port issues a write to its corresponding TLIOINTRn register in TLSB broadcast space.
TLIPINTR register and interrupts either (or both) of the CPUs as appropriate, based on their virtual node IDs. The interprocessor interrupt is cleared by a write to TLINTRSUM. 8.3.5 Module-Level Interrupts The CPU module uses the hardware interrupts provided as shown in Table 8-1. The handling of interrupts from I/O devices, the interval timer, and UARTs is under both hardware and PALcode control.
Glossary ADG Address gate array. Bank Smallest group of DRAMs that can be interleaved. A bank consists of one or more strings. Block 64 bytes of data within naturally aligned boundaries. CTL Control address interface. DDB DRAM data bus. The 576-bit bidirectional data bus that interfaces between the DRAM chips and the MDC gate arrays. DIGA Data interface gate array. Direct mapped I/O access A method of accessing I/O space on certain I/O bus adapters such as the integrated I/O section and the DWLPA.
FNS Fast, narrow, single-ended. FWD Fast, wide, differential. Internal Hose The connection (etch pathway) between the TLSB interface and the integrated I/O section of the KFTIA. HDR (DC296) Hose to I/O data path chip. Hose The interface between the I/O port and a single I/O bus adapter module. ICR (DC295) I/O control chip. IDR (DC294) I/O data path chip. Integrated I/O section Refers to all functions/hardware implemented from the internal hose to the SCSI, Ethernet, and FDDI ports. KFTHA I/O module.
String The smallest group of DRAMs (144 1/4M x 4) needed to store and retrieve 64 bytes of data per TLSB transaction. In some array implementations, the number of banks and strings can be equal, while in others there may be more strings than banks. TLSB The system bus for Digital AlphaServer 8200 and 8400 systems. Turbo Vortex bus The bus that interconnects the HDR, IDR, and ICR chips. Up HDR Hose to data path chip that receives transactions from the Up Hose.
Index A ABTCE, 7-8 Accessing remote I/O CSRs, 6-15 Accessing through I/O window space, 6-15 Accessing through mailboxes, 6-14 Access, remote I/O CSR, 6-14 Acknowledge Transmit Check Error bit, 7-11 ACKTCE, 7-11 ADDRESS, 7-21 Addressing, CSR, 2-25 Addressing, I/O port, 6-14 Address bank decode, 2-6 Address bits, 7-21 Address bit mapping, 2-7 Address bit swapping, 5-6, 5-7, 5-8 Address bus arbitration, 2-12 Address bus commands, 2-17 CSR read, 2-18 CSR write, 2-18 No-op, 2-17 Read, 2-17 Read bank lock, 2-17
A2MAPE1, 7-61 B Backup cache, 1-4, 4-2 BAE, 7-12 BANKV, 7-24 Bank address decoding, 2-9 Bank available flags, 5-4 Bank available status, 2-11 Bank available transition, 2-14 Bank busy check, 2-6 Bank busy violation, 6-71 Bank Busy Violation Error bit, 7-12 Bank collision, 2-15 Bank collision effect on priority, 6-34 Bank contention, CSR, 2-15 Bank decode in memory, 2-6 Bank lock and unlock, 2-15 Bank Lock Timeout bit, 7-11 Bank Lock Timeout Disable bit, 7-17 Bank match logic, 5-3 Bank Valid bit, 7-24 Base
Correctable Read Data Error bit, 7-9 Correctable Read Data Error Interrupt Disable bit, 7-18 Correctable Read ECC Error bit, 7-27 Correctable Write Data Error bit, 7-9 Correctable Write Data Error Interrupt Disable bit, 7-18 Correctable Write ECC Error bit, 7-27 CPU Halt Enable bit, 7-64 CPU Identification bit, 7-73 CPU Interrupt Mask register, 7-31 CPU interrupt rules, 8-2 CPU Mask bits, 7-31 CPU module address space, 3-6 CPU module block diagram, 3-2 CPU module components, 3-1 CPU Module Configuration reg
Data return format, 2-19 Data status errors, 2-41, 6-73 Data Status Error bit, 7-8 Data Syndrome 0 bit, 7-9 Data Syndrome 1 bit, 7-9 Data Syndrome 2 bit, 7-9 Data Syndrome 3 bit, 7-9 Data Timeout bit, 7-8 Data Transmitter During Error bit, 7-8 Data Transmit Disable bit, 7-17 Data Valid Transmit Check Error bit, 7-27 Data wrapping, 2-20 DCTCE, 7-8 DDR register, 7-106 DECchip 21164A features, 3-2 overview, 1-3 Decrement queue counter, 3-11 DEDA, 7-99 DEFAULT, 7-91 Default interleave, 4-15 Default Power Up Sta
Drive TLSB Bad bit, 7-81 DRIVE_BAD, 7-81 DRIVE_CONWIN, 7-81 DRIVE_RUN, 7-81 DSE, 7-8 DS0, 7-9 DS1, 7-9 DS2, 7-9 DS3, 7-9 DTag CPU bit, 7-48 DTag Data Entry bits, 7-50 DTag Data Parity bit, 7-50 DTag Data Parity Error bit, 7-55 DTag Data register, 7-50 DTag Read bit, 7-48 DTag Status bits, 7-51 DTag Status Parity bit, 7-51 DTag Status Parity Error bit, 7-55 DTag Status register, 7-51 DTag Write bit, 7-48, 7-49 DTAG_DATA<38:20>, 7-50 DTAG_DAT_PAR, 7-50 DTCP, 7-48 DTDE, 7-8 DTDPE, 7-55 DTO, 7-8 DTOD, 7-17 DTR,
False arbitration, 2-7, 2-14 Fatal Data Transmit Check Error bit, 7-8 Fatal No Acknowledge Error bit, 7-10 Fault Disable bit, 7-52 FAULT_DIS, 7-52 FBANK, 7-25 FCAPE, 7-101 FCMD, 7-25 FDBE, 7-48 FDDI registers, 7-142 FDE<3:0>, 7-48 FDTCE, 7-8 Fixed high mode, 6-33 Fixed low mode, 6-33 Flash ROMs, 3-4 Flow control, 3-10 FNAE, 7-10 Force Bank Busy Error bit, 7-123 Force Column Address Par Err bit, 7-101 Force CSR Bus Addr Par Err bit, 7-135 Force CSR Bus Data Par Err bit, 7-135 Force data error bit, 7-48 Force
ICCNSE register, 7-117 ICCWTR register, 7-127 ICC and IDP internal illogical errors, 6-77 ICC CSR Bus Par Err bit, 7-118 ICC Internal Error bit, 7-118 ICFR, 7-108 ICR_CSR_BUS_PE, 7-118 ICR_IE, 7-118 IDENT, 7-30 Identification Vector bits, 7-30 IDPDR register, 7-133 IDPMSR Data Path Mode Select register, 7-138 IDPMSR register, 7-138 IDPNSE register, 7-128 IDPVR register, 7-137 IDR Command Par Err bit, 7-130 IDR CSR Bus Par Err bit, 7-129 IDR Internal Error bit, 7-129 IDR Up Vortex Error bits, 7-130 IDR_CMD_P
I/O Control Chip Node-Specific Error register, 7-117 I/O Ctrl Chip Window Transaction register, 7-127 I/O Data Path Diagnostic register, 7-133 I/O Data Path Node Specific Error register, 7-128 I/O Data Path Vector register, 7-137 I/O interrupt mechanism, 8-3 I/O Interrupt registers, 7-36 I/O port addressing, 6-14 I/O port arbitration, node 8, 6-31 I/O port block diagram, 6-3 I/O port components, 6-2 I/O port CSR read/write transactions, 6-28 I/O port errors, hard, 6-75 I/O port errors, hard internal, 6-66 I
Memory mapping register error, 3-18, 6-71 Memory Mapping Register Error bit, 7-10 memory module capacity, 7-105 Memory module, overview, 1-4 Memory organization, 4-13 Memory refresh, 4-16 Memory sections, 4-10 Memory self-test, 4-16 Memory self-test error registers, 4-18 Memory space, 3-7 Memory specific registers, 7-85 Memory transactions, 4-16 Memory, main, 4-9 Merge register, 5-17 MER register, 7-97 Minimum latency mode, 6-31 MIR register, 7-87 MMG Error register, 7-59 MMG to ADG Addr Par Err #0, 7-56 MM
CPU Module Configuration, 7-52 Data Diagnostic, 7-106 Data Mover Command, 7-72 Data Mover Destination Address, 7-76 Data Mover Source Address, 7-75 Diagnostic Setup, 7-47 DIGA Communications Test, 7-69 DIGA Error, 7-57 DTag Data, 7-50 DTag Status, 7-51 GBUS$LED, 7-78 GBUS$MISCR, 7-79 GBUS$MISCW, 7-81 GBUS$SERNUM, 7-83 GBUS$TLSBRST, 7-82 GBUS$WHAMI, 7-77 Information Base Repair, 7-140 Interrupt Mask, 7-63 Interrupt Source, 7-65 I/O Control Chip Diagnostic, 7-122 I/O Control Chip Mode Select, 7-112 I/O Contro
Self-Test Error in MDI0 bit, 7-96 Self-Test Error in MDI1 bit, 7-96 Self-Test Error in MDI2 bit, 7-96 Self-Test Error in MDI3 bit, 7-96 Self-Test Error register, 7-95 Self-Test error reporting, 4-18 Self-Test Failing Address Range bits, 7-93 Self-Test Fail A bit, 7-16 Self-Test Fail B bit, 7-16 Self-test modes, memory, 4-17 Self-test operation, memory, 4-18 Self-Test Passed bit, 7-83 Self-Test Pattern Select bit, 7-107 Self-test performance, 4-19 Self-test times, 4-19 Self-test, memory, 4-16 SEND_DATA timeo
TLEPMERR register, 7-59 TLEP_VMG register, 7-62 TLESR0-3 registers, 7-26 TLFADR0-1 registers, 7-24 TLILID0-3 registers, 7-30 TLINTRMASK register, 7-63 TLINTRSUM register, 7-65 TLIOINTR4-8 registers, 7-36 TLIPINTR register, 7-35 TLMBPR register, 7-32 TLMBPR register map, 6-15 TLMCR register, 7-43 TLMMR0-7 registers, 7-21 TLMODCONFIG register, 7-52 TLRDRD register, 2-33, 7-41 TLRDRE register, 7-42 TLRMDQRX register, 7-39 TLRMDQR8 register, 7-40 TLSB address transmit check errors, 6-70 TLSB arbitration, 2-2, 6
UECC, 7-27 Uncorrectable Data Error bit, 7-10 Uncorrectable ECC Error bit, 7-27 Unexpected acknowledge, 6-71 Unexpected Acknowledge bit, 7-8 Unexpected acknowledge error, 3-18 Unexpected mailbox status packet, 6-77 Unexpected Mailbox Status Packet Received bits, 7-121 UNIX, 1-7 UN_MBX_STAT, 7-121 UPCTL<3:0> encoding, 6-39 Up HDP Internal Error bit, 7-120 Up Hose, 6-35 Up Hose errors, 6-75 Up Hose FIFI Overflow bits, 7-121 Up Hose Packet Error bits, 7-121 Up Hose packet specifications, 6-52 Up Hose Parity Er
