User`s manual
Table 3-12
(Cont)
Line Progress Secondary Register Bit Assignments
Bit( s)
07
08-09
10
11-12
13-15
Designation
Resynchronization
Rag Expected
Send
BCC
Next Transmit Mode
on Marked Byte
Count = 0
3.4
CONTROL
BYTE
FORMAT
Function
(Not intended
[or
access by the PDP-II program.)
Set to one
by the Microprocessor whenever a
resynchronization cycle starts for the associated
line receiver as
commanded
by
Line State
01.
Oeared
by the Microprocessor when all characters
stored
in the
RC
Silo for the associated line have
been removed. This bit inhibits transfer
of
RC
Silo
characters designated
for the associated line to the
Unibus until the Resynchronization Flag character
reaches the
bottom
(output)
of
the RC Silo.
Unused
When a marked transmitter byte
count
reaches zero,
this bit
is
examined by the Microprocessor.
If
this
bit has been set
to
one by the PDP-II program, the
Microprocessor sets Line Progress
00
(Send
BCCI
Next) to one for the associated line. The Micro-
processor
then
transmits
the
first
block
character
(BCC I ) after the character which caused this byte
cuulIl
Lu
gu
Lu
Lew.
If
t:llht:f
CRC-lll
uI
CRC-CCITT
is
the selected
protocol,
the Microprocessor transmits
the second block check character
(BCC2) after
transmission
of
BCCI.
Unused
When a marked transmitter
byte
count
reaches zero,
the Microprocessor transfers these bits
to
bit
00-02
of
the Transmitter Mode Bits secondary register
to
set the mode for the
next
character(s)
to
be trans-
mitted.
Read/Write
Read
Read or Write
Read or Write
Control
byte bit assignments (Table 3-13),
are
based
on
the
structure
of
the
DV
II
interpretation
logic,
and
are
arranged
so
that
the same
control
bytes can
be
used for
both
transmission
and
reception,
provided
that:
2.
The
same
characters
are
included in
the
BCC for
both
transmit
or
receive.
I f the
protocol
being executed does
not
have
the
above
characteristics,
separate
control
tables for
transmit
and
receive
may
be established by
setting
different values in Receive
Control
Table
Base
Address
and
Transmit
Control
Table
Base
Address
secondary
registers.
Control
byte
formats
for
trans-
mission
and
reception
are
shown
in
Figure
3-2.
1.
The
protocol
progresses from
mode
to
mode
in a symmetrical fashion for
both
transmit
and
receive,
and
3-39