User`s manual
Table 3-12 (Cont)
Line Progress Secondary Register Bit Assignments
Bit(s)
Designation
Function
Read/Write
05
Expect BCCI
(Not intended for access by the PDP-II program.)
Read
Set
to
one by the Microprocessor whenever (1) Line
State bit
II
(Expect BCC) has been set
to
one by
the PDP-II program and a marked byte count has
reached zero, or
(2)
a receive control byte has been
fetched with bit
03 (Expect BCC) set
to
one. The
next received character
is
then interpreted
as
the
first block check character
(BCCI)
and a
BCC
calcu-
lation is performed. If
LRC-8
is
the selected block
check
type,
the Microprocessor
I.
places the
OR
of
the high and low bytes
of
the
accumulated
BCC
into the RIC register with
the line number and interrupt code
0101.
2. writes a control byte with bit 04 (character
discard) set
to
one,
into
the Control Byte
secondary register
to
inhibit storage
of
the
BCC, and
3. sets
SCR
07
to one
to
interrupt the PDP-II
program.
If either
CRC-16 or CRC-CCITT
is
the selected block
check type
(both
BCCI and BCC2 required), the
Microprocessor sets
line
Progress
06
(Expect BCC2)
and does
not
perform steps
I,
2, and 3 until after
BCC2
is
received.
06
Expect BCC2 Next
(Not intended for access by the PDP-II program.)
Read
Set
to
one by the Microprocessor whenever
line
Progress 05 (Expect BCCI) is set from one to zero
during a character reception cycle and either
CRC-J6
or CRC-CCITT
is
the selected block check type. The
next received character
is
then interpreted as the
second
BCC
(BCC2), a
BCC
calculation
is
performed,
and the Microprocessor proceeds
as
described in
steps
I,
2, and 3 for
line
Progress bit 05.
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