User`s manual
3.3.9 Transmitter Control Table Base Address (1000)
The
Transmitter
Control
Table
Base Address second-
ary register contains
the
18-bit address
of
the
trans-
mitter
control
table for the associated line.
The
extended address bits
are
initially ioaded from
SCR
04-05
to
provide the 18-bit
address
capability.
The
contents
of
this register
are
used by the Micro-
processor in
the
computation
of
the
control
byte
addresses for
transmitted
characters.
3.3.10 Receit'er Control Table Base Address (IO(H)
The
Receiver
Control
Table
Base Address
secondary
register contains
the
18-bit address
of
the
receiver
control
table for the associated line.
The
extended
address bits are initially
loaded
from
SCR
04-05
to
provide the 18-bit address capability. The
contents
of
this register
are
used by the Microprocessor in the
computation
of
the
control
byte addresses for the
received characters.
3.3.11 Line Protocol Parameters (1010)
The
Line Protocol Parameters secondary register
contains
the
transmitter
Data
Link Escape
(OLE)
character
when required by the associated line pro-
tocol, plus l:ontrol
bits
to
implement
protocol
requirements
and
handling
of
sync characters.
The
PO
P-II
program
writes the
data
in this register for
reference by the microprogram. Bit assignments
are
described in detail
in
Table 3-10.
3.3.12 Line State
(lOll)
The
Line State secondary register is used by
the
PDP-
II
program
and
the Microprocessor
to
control
and
monitor
line activities in executing the selected
pro-
tocol.
This
register
is
also used by the
PDP-II
pro-
gram
to
store mode change
and
BCC
anticipation
bits for reference by the Microprocessor when a
marked
Receiver Byte
Count
reaches zero, as dis-
cussed in Section 3.1. Bit assignments
are
described in
detail
in
Table 3-11.
3.3.13 Transmitter Mode Bits (1100)
The
Transmitter
Mode
Bits secondary register con-
tain the 3-bit mode selection field (in bits
00-02)
which determines the
transmitter
control
table
to
be
used for controlling transmission on the associated
line.
3.3.14 Receit'er Mode Bits (1101)
The
Receiver
Mode
Bits secondary register
contains
the 3-bit mode selection field (in bits
00-02)
which
3-33
determines the receiver control table
to
be
used for
control1ing reception
on
the associated line.
3.3.15 Line Progress (1110)
The
Line Progress secondary register
contains
bits set
and
referenced by
the
Microprocessor
to
control
and
monitor
activities on the associated line in executing
the selected
protocol
(these bits are
not
intended for
access by the
PDP-II
program).
This register also
stores
mode
change
and
Bee
transmission
control
bits, as set by the
PDP-II
program,
for use by the
Microprocessor when a
marked
Transmitter
Byte
Count
reaches zero, as discussed in Section 3.1. Line
Progress register bit assignments
are
described in
detail in Table 3-12.
3.3.16 Receit'er Control Byte Holding (1111)
The
Receiver
Control
Byte H aiding secondary regis-
ter provides storage for
the
Receiver
Control
Byte
in
bits 00-07.
The
PDP-II
program
may set a
control
byte into this register while responding
to
a
DVII
receiver special
character
interrupt. When the
PDP-
II
program
signals the
DVII
that
its
interrupt
response
is
complete
(SCR
08=
I), the Micro-
prOl:essor uses the
control
byte
in
this register to con-
trol the disposition
of
the interrupting
character
in
the
RIC
register.
The
Microprocessor may also use this register
to
write
control
bytes
that
specify
character
discard
only, if an
error
condition
or
data
block
boundary
condition
caused the interrupt; the existing mode
specified
in
the
control
byte
is
not
altered.
The
PDP-
II
program
should
not
write this register except dur-
ing initialization
or
interrupt
response cycles. Receiv-
er
Control
Byte format
is
shown
in
Figure 3-4.
If
the
PDP-II
programmer
so
desires, the
generation
of
receiver interrupts may be limited
to
only those
cases where the
PDP-II
program
wishes notification
that
a
particular
character
has arrived,
rather
than
have the
PDP-II
program
change
the
character
proc-
essing directions specified in the
control
byte. In these
circumstances, the
PO
P-ll
program
may direct
that
character
processing resume (set
SCR
08 =
I)
without
changing the
control
byte stored in the Receiver
Con-
trol Byte Handling register.
This
is
possible because
the
control
byte
is
stored
with its bit 00 (generate
interrupt)
cleared.