User`s manual
3.3.3 Transmitter Alternate Current Address (0010)
The
Transmitter
Alternate
Current
Address
register
has exactly
the
same
function as the
Transmitter
Principal
Current
Address
register described in
Para-
graph
3.3.1.
This
register is
incremented
by
one
with
each
character
transmitted
by
the
DVII
on
the
asso-
ciated line if
the
alternate
message table
is
being used
(Line
State
secondary
register
bit
07 set
to
one).
When
the
Transmitter
Alternate
Byte
Count
(second-
ary register 0011) for the associated line reaches zero,
an
interrupt
code is set in the
NPR
Status
register.
Transmission
continues
using
the
Transmitter
Princi-
pal
Current
Address
for
this
line
(secondary
register
0001),
provided
that
the
Transmitter
GO
bit in
the
Line
State
secondary
register for the same line is still
set
to
one.
3.3.4 Transmitter Alternate Byte Count (0011)
The
Transmitter
Alternate
Byte
Count
secondary
register
contains
a IS-bit
word
that
is the 2's com-
plement
of
the
number
of
bytes (characters) remain-
ing
to
be
transmitted
on
the associated line.
The
16th
bit
(bit
15) is used by
the
PDP-II
program
to
enable
change
of
mode
and/or
BCC
transmission,
based
on
reaching a zero byte
count
during
transmission.
When
bit
15
is
set
to
zero by
the
PDP-II
program,
bits 13-15
of
the
Line Progress secondary register for
this line will
control
the
transmission
mode
when the
alternate
byte
count
reaches zero; also,
the
BCC will
be
transmitted
if
Line Progress bit
10
is
set
to
one.
When
bit
IS
is
set
to
one
by the
PO
P-II
program,
bits
00-02
of
the
Transmitter
Mode
Bits secondary regis-
ter
continue
to
control
the
line transmission mode. A
byte
count
with bit IS set
to
zero
(at
the time
that
the
byte
count
is loaded by
the
PDP-II
program)
is
referred
to
as
a
··marked"
byte
count.
This
register
is
incremented by
one
with each
charac-
ter
transmitted
on
the associated line by
the
DVII
if
the
alternate
message
table
is
being used (Line
State
secondary
register bit 07 set
to
one).
When
this regis-
ter reaches zero, transmission
continues
using the
Transmitter
Principal Byte
Count
for this line
if
the
Transmitter
GO
bit in the Line
State
secondary regis-
ter
is
still set
to
one.
3.3.5 Receit'er Current Address (0100)
The
Receiver
Current
Address
register
contains
the
18-bit
core
memory
address
for
storage
of
the
next
character
to
be
received
on
the
associated
line.
The
extended
address
bits
are
initially
loaded
from
SCR
04-05
to
provide
the
18-bit
address
capability.
This
register
is
incremented by
one
with
each
character
received on
the
associated line by the
DVII.
3.3.6 Receiver Byte Count (0 101)
The
Receiver Byte
Count
secondary register
contains
a IS-bit word
that
is
the
2's
complement
of
the
num-
ber
of
bytes (characters) remaining to be received
on
the associated line.
The
16th bit (bit
15)
is used by
the
PD
P-II
program
to
enable
change
of
mode
and/or
BCC
anticipation,
based on reaching a zero byte
count
during
reception.
When
bit
15
is
set
to
zero by
the
PDP-II
program,
bits 13-15
of
the Line
State
sec-
ondary
register for this line will
control
the reception
mode
when
the
byte
count
reaches zero; also, the
BCC will be expected
if
Line
State
bit
10
is
set
to
one.
When
bit
15
is
set
to
one by the
PDP-II
program,
bits
00-02
of
the Receiver
Mode
Bits
secondary
register
continue
to
control
the
line reception mode. A byte
count
with bit
15
set to zero
(at
the
time
the
byte
count
is
loaded
by the
PDP-II
program)
is
referred
to
as a
"marked"
byte
count.
When this register reaches
zero, an
interrupt
code
is
set in the
RIC
register
and
the DV II
stops
transferring received
characters
to
core
memory.
3.3.7 Transmitter Accumulated Block Check
Character
(OlIO)
The
Transmitter
Accumulated
Block
Check
second-
ary register
contains
the
continuously-computed
BCC (specified by
the
Line
Protocol
Parameters
sec-
ondary
register)
to
enable
destination
stations
to
check integrity
of
transmission
on
the associated line.
Characters
to
be
included in
the
block check calcu-
lation are specified by bit
03
of
the
Transmitter
Con-
trol Bytes for each character.
The
contents
of
this
register are
transmitted
as two sequential bytes, low-
order
eight bits first (except when
LRC-8
is
the
selected block check type, in which case a single byte
is
transmitted).
The
DV
11
automatically
clears this
register
to
zero
after
transmitting
its contents.
NOTE
The
DVII
computes CRC-16 and
CRC-CCITT
on a
byte-at-a-time basis (parallel), thus the character
length must be eight bits. LRC-8 may
be
selected for
characters
of
5, 6, 7, or 8 bits.
3.3.8 Receiver Accumulated Block Check Character
(0111 )
The
Receiver Accum ulated Block
Check
secondary
register
contains
the
continuously-computed
BCC
(specified by
the
Line Protocol
Parameters
secondary
register) for checking integrity
of
data
received
on
the
associated line.
Characters
to
be included in
the
block
check calculation
are
specified by bit 03
of
the
Receiver
Control
Byte for
that
character.
The
PDP-
II
program
should
clear this register if
the
accumu-
lated block check
at
the
end
of
the
mess1ge
is
non-
zero.
3-32