User`s manual
Table 3-9
(Cont)
Line
Status
Register Bit Assignments
Bit
Designation
Function
Read/Write
06
CO
(Carrier
On)
(detected)
Set
to
1 whenever the CO line from the
modem
selected
by bits
0-3
of
the
CSR is
ON,
provided
that
the Line En
bit
for
that
modem
is present and
that
the received signal
is
present for demodulation.
Read only
07
RING
Set
to
1 whenever the RING line from
the
modem
selected
by
bits
0-3
of
the CSR
is
ON,
provided
that
the Line En
bit
for
that
modem
has been set. Indicates a remote modem
is
signalling
the
local
modem.
Read only
3.3
INDIRECTLY
ADDRESSABLE
(SECOND-
ARY)
REGISTERS
The
secondary
registers
make
up
the
RAM
of
the
DVII
and
may
be
accessed
by
the
PDP-ll
program
via
the
SRS
and
the
SAR,
as
described
in
Section
3.2.
The
PDP-II
program
must
clear
(or
properly
set
up)
all
secondary
registers
before
setting
SCR
00
(Micro-
orocessor
GO),
Because
the
RAM
is
volatile,
second-
ary
register
contents
must
be
re-established
in
the
event
of
power
failure.
Sixteen
secondary
registers,
summarized
in
Table
3-1,
are
provided
for
each
of
the
16
data
lines,
making
a
total
of
256
secondary
registers.
Secondary
register
formats
are
shown
in
Figure
3-4.
NOTE
The
Secondary
Registers
are
NOT
cleared
by
Initialize.
3.3.1
Transmitter
Principal
Current
Address
(0000)
The
Transmitter
Principal
Current
Address
second-
ary
register
contains
the
18-bit
core
memory
address
of
the
next
character
to
be
transmitted
on
the
associ-
ated
line.
The
extended
address
bits
are
initially
loaded
from
SCR
04-05
to
provide
the
18-bit
address
capability.
This
register is
incremented
by
one
with
each
character
transmitted
on
the
associated
line
by
the
DV
II
if
the
principal
message
table
is
being
used
(Line
State
secondary
register
bit
07
set
to
zero).
When
the
transmitter
Principal
Byte
Count
(second-
ary
register
0001)
for
the
same
line
reaches
zero,
an
interrupt
code
is
set
in
the
NPR
Status
register.
3-29
Transmission
continues,
using
the
Transmitter
Alter-
nate
Current
Address
for
this
line
(secondary
register
000
I),
provided
that
the
Transmitter
GO
bit
in
the
Line
State
secondary
register
for
this
line is still
set
to
one.
3.3.2
Transmitter
Principal
Byte
Count
(0001)
The
Tran<;mitter Principal Byte
Count
<;econdary reg-
ister
contains
a
IS-bit
word
that
is
the
2's
com-
plemen
t
of
the
n urn
ber
of
bytes
(characters)
remaining
to
be
transmitted
on
the
associated
line.
The
16th
bit
(bit
15) is
used
by
the
PDP-II
program
to
enable
change
of
mode
and/or
BeC
transmission,
based
on
reaching
a
zero
byte
count
during
transmis-
sion.
When
bit
15
is
set
to
zero
by
the
PDP-II
pro-
gram,
bits
13-15
of
the
Line
Progress
secondary
register
for
this
line
will
control
the
transmission
mode
when
the
principal
byte
count
reaches
zero;
also,
the
BCC
will
be
transmitted
if
Line
Progress
bit
lOis
set
to
one.
When
bit
IS
is
set
to
one
by
the
PDP-
II
program,
bits
00-02
of
the
Transmitter
Mode
Bits
secondary
register
continue
to
control
the
line
trans-
mission
mode.
A
byte
count
with
bit
IS
set
to
zero
(at
the
time
the
byte
count
is
loaded
by
the
PDP-II
pro-
gram)
is
referred
to
as
a
"marked"
byte
count.
This
register
is
incremented
by
one
with
each
charac-
ter
transmitted
on
the
associated
line
by
the
DVII
if
the
principal
message
table
is
being
used
(Line
State
07 set
to
zero).
When
this
register
reaches
zero,
trans-
mission
continues
(using
the
Transmitter
Alternate
Byte
Count
for
this
line)
if
the
Transmitter
GO
bit
in
the
Line
State
secondary
register
is still
set
to
one.