User`s manual
Bit(s)
00-03
04
05
06
Designation
LINE (Line Number)
BUSY
SCAN
EN
(Scan Enable)
INTER EN
(Interrupt
Enable)
Table 3-8
Control
Status
Register Bit Assignments
Function
Binary address
of
one
of
16 modems:
Bit 3
n
v
o
2
n
v
o
n
v
o
o
n
v
Line No.
n
v
15
Cleared
to
0000
by Initialize or Clr Scan (bit
11
of
CSR). Sixteen microseconds ±IO% settling time is
required.
This portion
of
the CSR is a presettable binary
counter;
thus, it may be loaded directly
by
the
PDP-II program
to
address a selected data line,
or
advanced
by
SCAN
EN
(CSR bit 5) or STEP (CSR
bit
8)
to
address sequential data lines.
Set
to
1 whenever modems are being cyclically
scanned
or
a Clr Scan (CSR bit 11) is being
executed.
Causes cyclical scanning
of
status lines from all
enabled modems when set to 1
if
Done (CSR bit
7)
is
set
to
O.
Scanning stops and Done
is
set
to
1 when a status transition is detected. A 1.2
microsecond period
is
required for scanning
to
come
to
a halt when the PDP-II program changes
this bit from 1
to
0;
therefore, Busy (CSR bit
4)
must be tested for its zero state before changing
the line
number
(CSR bits
0-3)
to
ensure
that
all detected transitions are serviced. Cleared
by
Initialize
and
Clr
Scan
(CSR bit 11).
Enables Done signal from
CSR bit 7
to
cause a
PDP-II
interrupt
on
priority four when set
to
1.
Cleared
by
Initialize and Clr Scan (CSR bit 11).
3-25
Read/Write
Read
or
Write
Read only
Read
or
Write
Read
or
Write