User`s manual
Table 3-7
Transmit Function Interrupt Conditions
Code Set in NSR
OS-II
Meaning
Transmiiter principal current address specified a non-existent memory loca-
tion (NXM).
a
a a
Transmitter principal byte count
is
equal
to
zero.
a a
a Transmitter alternate current address specified a non-existent memory loca-
tion
(NXM).
a 0
Transmitter alternate byte count
is
equal to zero.
a 0 0
An
attempted control byte fetch by the DVII produced a non-existent mem-
ory condition or a memory parity error. (The specific error is set in the Une
State secondary register.)
SRS
00-03
are
also used
to
select line
control
storage
for
loading
from
the
Line
Control
Register.
CAUTION
Do
not change the contents
of
SRS
without checking
that
LCR
IS is cleared, indicating
that
any outstanding
LCR
load
to
the line
cards
has been completed.
3.2.8 Secondary Register Access Register
(SAR)
The
Secondary
Register Access Register provides
the
PO
P-II
program
with
direct
access
to
the
secondary
register selected
by
the
SRS
register.
Loading
or
read-
ing
the
SAR
is
equivalent
to
loading
or
reading
the
secondary
register
addressed
by
SRS
00-03
and
08-11.
3.2.9
Modem
Control Registers
PO
P-II
program
control
of
the
line
modems
is
accomplished
through
the
Control
Status
Register
(CSR)
and
the
Line
Status
Register
(LSR)
in
the
Modem
Control
Unit
(MCU)
of
the
DVI1.
The
CSR
controls
data
line
or
modem
selection
and
operating
mode
(interrupt
or
non-interrupt)
of
the
MCU,
and
enables
the
detection
of
changes
in
modem
status
by
the
PDP-II
program.
The
LSR
routes
control
bits
provided
by
the
PDP-II
program
to
the
modems
and
transfers
modem
status
bits
to
the
Unibus
for
the
modem(s)
selected via
the
CSR.
To
enable
anyone
of
the
16
lines,
the
PDP-II
program
sets
the
selected line
3-24
number
in
the
CSR,
then
sets
the
Line
Enable
bit
in
the
LSR.
Formats
for
the
CSR
and
LSR
are
displayed in Fig-
ure 3-3. Bit assignments
are
described in detail in
Tables
3-8
and
3-9, respectively.
Some
bit
assign-
ments
have
dual
definitions
to
reflect
the
type
of
modem
that
is
being
controlled
(i.e.,
synchronous
vs
asynchronous).
Tables
3-8
and
3-9 define
each
bit
assignment
as
it applies
to
both
modem
types.
The
interrupt
mode
is
set
for all
enabled
lines by set-
ting
CSR
05
and
06
each
to
one.
eSR
05 (Scan
Enable) causes
the
MeU
to
scan
the
enabled
modems
cyclically
to
detect
a
change
or
transition
in
one
of
the
modem
status
bits.
When
a
transition
is detected,
scanning
is
stopped,
the
condition
causing
the
transi-
tion is
set
in
the
eSR
12-15 field,
the
line
number
for
the
signalling
modem
is available in
eSR
00-03,
CSR
07
(Done
bit) is set
to
one,
and
the
PDP-ll
program
is
interrupted.
The
non-interrupt
mode
is feasible if
only
one
modem
is
to
be
monitored
for
activity
at
one
time.
The
line
number
for
the
modem
is set in
the
eSR
and
modem
status
bits
LSR
04-07
are
continuously
sampled
by
the
PDP-II
program.
When
one
of
these
status
bits
becomes
set
to
one,
the
PDP-II
program
may
respond
by
setting a 03.