User`s manual
Bit(s)
Designation
Table
3-4
(Cont)
Une Control
Reg~ter
Bit Assignments
(For Asynchronous Line Cards)
Function Read/Write
Asynchronous Line Card Maintenance Register
09,10
11
12-14
15
Maintenance
Register
Selection
Code
11
Maintenance
Internal
Mode
Control Strobe
For the line number specified by SRS
00-03,
the
code
of
11
specifies writing into the Maintenance
register at
LCR
15
set
time.
This bit, when set, loops the transmitter's serial output
lead to the receiver's serial input lead.
While
operating
in maintenance mode, the EIA transmit data leads,
EIA received data leads, and the remote Data Set busy
features
are
disabled. Normal operating mode
is
assumed when this bit
is
cleared.
Unused
When
set
to
a one, strobes the Maintenance register
bit
11
into storage for the line specified
in
SRS
00-03,
then clears itself.
May
be set at the
same
time
as
the bit that it strobes into storage.
Write
Write
Write
Interrupt-causing conditions
and
associated line
numbers are stacked in the 64 entry first-in, first-out
silo buffer
and
dropped
into the
NSR
output
as each
prior
entry
is
read by the
PDP-II
program. Each time
a new entry is dropped into
NSR
output,
NSR
15
is
set
to
indicate the presence
of
valid
data
and
SCR
15
is
set
to
request an interrupt. Each time
an
NSR
entry
is
read by the
PO
P-II
program,
NSR
15
and
SCR
15
are reset
to
zero.
NSR
15
is also set
to
zero by
Initialize. (The
other
NSR
bits
are
not
reset
to
zero
by initialize.)
3.2.6 Special Functions Register (SFR)
The
Special Functions Register
is
used for mainte-
nance only.
3.2.7 Secondary Register Selection Register (SRS)
The
Secondary Register Selection Register provides
for
PDP-II
program access
to
the secondary registers
in
the DV II
RAM.
To
address a secondary register,
the PO
P-II
program sets the 8-bit
RAM
address,
consisting
of
the 4-bit line number, plus the 4-bit reg-
ister selection code, in SRS 00-03 and SRS 08-11,
respectively. Loading
or
reading the SRS
is
then
accomplished by loading
or
reading the SAR. Inter-
rupt service routines must save the contents
of
the
SRS.
The
NSR
format
is
shown in Figure 3-3. Transmis-
sion interrupt codes
are
described in Table 3-7.
3.2.S Resened Register
Reserved for future system requirements.
3-20
The
4-bit line selection code
in
SRS 00-03 provides
for selection
of
the
16
data
lines. The 4-bit register
selection code
in
SRS 08-11 provides for selection
of
the
16
secondary registers supplied for each data line.