User`s manual

Bit(s)
09,10
11
12
13
14
15
Designation
Table 3-4 (Cont)
Line Control Register Bit Assignments
(For Asynchronous Line Cards)
Function
Asynchronous Line Card Primary Register
Primary Register
Selection
Code 00
Half Duplex!
Full Duplex
Even Parity
Receiver Enable
Break
Control Strobe
For the line number selected by SRS 00-03, the
code of 00 specifies writing into the Primary
register at LCR 15 set time.
This bit, when set, conditions the line to operate in
half duplex mode. If this bit is cleared, the line is
conditioned to operate in full duplex mode. When
operating in half duplex mode, the selected receiver
is blinded during transmission of a character.
This bit, when set, generates characters with even
parity on the line and expects received characters
to have even parity. If this bit is cleared, characters
of odd parity are generated on the line and received
characters are expected to have odd parity. The
state of this bit is immaterial if the Parity Enable
bit (Format register bit 14) is not set. This bit
must be ~onditioned prior tu loading the Furmat
Register.
This bit must be set before the receiver l<;>gic can
assemble characters from the serial input line. When
this bit is set, Receiver Active (Line State Bit 00)
is subsequently set. To shut down reception on a
line, the program should first clear Receiver Enable
and the set Receiver Resynchrqnize (Line State
Bit 01). The program must wait one character
interval after shutdown before restarting a line.
This bit, when set, forces a space on that line's
output causing a break condition. The break con-
dition may be timed by sending characters during
the break interval, since these characters never
reach the EIA line.
When set to a one, strobes the Primary Register
bits 11, 12, 13, 14 into storage for the line speci-
fied in SRS 00-03, then clears itself. May be set
at the same time as the bits that it strobes into
storage.
3-17
Read/Write
Write
Write
Write
Write
Write
Write