User`s manual
Table 3-3 (Cont)
Line Control
Register Bit Assignments
(For Synchronous Line Cards)
Bit(s)
Designation
Function Read/Write
15
Control Strobe
When
set
to
one, strobes
LCR
13
into control
storage for the line set in
SRS
00-03
and strobes
LCR 09, 10, 11, 12, 14 into control storage for
Write
the 4-line group set in SRS
02-03,
then clears
itself.
May
be
set at the same time
as
the
LCR
bits that it strobes into storage for the selected
line or line group.
The
following
LCR
bit descriptions apply only
to
those lines associated with an asynchronous line card.
For
asynchronous line cards, each line has four 4-bit
registers associated with it, each
of
which may be
loaded by addressing the
LCR
with
appropriate
reg-
ister selection bits set in
LCR
09
and
10, in addition
to the line selection bits set in SRS 00-03.
The
four
registers associated with each line are called the
""Primary," ""Format,"
"Baud
Rate,"
and
"Mainte-
nance" registers and are selected by
LCR
10-09 codes
of
00,
0),
)0,
and
II
respectively. While
the
bit
assignments are described in detail in Table 3-4, it
can
be noted here
that
LCR
15
(Line
Control
Strobe)
functions the same for asynchronous line
cards
as it
does for synchronous line cards
and
that
the
cautions
expressed above with regard
to
LCR
bits
09-14
are
similarly valid for the asynchronous case.
The
LCR
~ormat
for asynchronous line
cards
is displayed in
Figure 3-3. Bit assignments are described in detail in
Table 3-4.
3.2.3 Receiver Interrupt Character Register
(RIC)
The Receiver
Interrupt
Character
Register is a read-
only register which stores the character
that
caused
the
PD
P-) I
program
interrupt,
the
line
number
on
which the character was received,
and
the code speci-
fying
the
reason for the interrupt. This register is
cleared by Initialize.
3-15
The
format
of
the
RIC
is
shown in Figure 3-3. Specif-
ic
bit
assignments for the
RIC
are as follows:
Bits
()()~7:
This field contains
the
inter-
rupting character, right-justified. Bit 00
is
the
least significant bit.
On
parity-equipped syn-
chronous
characters
of
less
than
eight bits, the
parity
hit
will
appear
immediately
to
the
left
of
the highest
order
bit in
the
character.
Bits
08-1/:
This field contains the line
num-
ber
on
which the interrupting character was
received. Bit eight is
the
least significant bit.
Bits 12-15: This field contains the
code
speci-
fying the reason for the interrupt. Refer
to
Tables 3-5 and 3-6 for code meanings.
3.2.4
NPR
Status
Register (NSR)
The
NPR
Status Register is a 64-level
"read-once"
silo; that is, a read
of
this silo
"empties"
it
of
its old-
est entry (destructive read),
and
any new
data
"falls"
into the silo
output
if
new
data
is waiting when a read
is
completed.
The
NSR
is read-only register which
identifies
(I)
interrupt-causing conditions
that
occur
during
character
transmission
and
(2) the line n um-
ber on which
the
interrupt
occurred.