User`s manual

Table 3-2
System Control Register Bit Assignments
Bit(s) Designation
Function
Read/Write
00
Microprocessor GO
When set to one, enables the Microprocessor to Read or Write
operate the
DVll Data Handling Section. Must
be set
to one to enable DVII to perform any
functions
other than modem control. Cleared
by Initialize.
01-03
(Maintenance) .
04-05
Extended Address
The contents
of these bits as set by the PDP-II
Write
program form bits
16 and 17, respectively, of
any current address or control table base address
loaded by the PDP-II program into a secondary
register for the line selected by SRS
00-03.
These bits must be set before loading the
Secondary
register. These bits are read/write,
but when read reflect only the values of SCR
04-05, and not the values of address bits 16 and
17 for the selected line. (Refer to the discussion
of Line Control Register bits 04-05.) Thus, an
interrupt service routine saving the contents
of
these bits will store bits 04-05 exactly as set by
the PDP-II program.
Cleared by Initialize.
06 Receiver Interrupt When set to one by the PDP-II program, enables
Read or Write
the Microprocessor to interrupt the PDP-II pro-
gram by setting a one in
SCR 07. Cleared by
Initialize.
07
Receiver Interrupt Set to one by the DVII to request a PDP-II pro- Read or R/W
(Vector A)
gram interrupt occurring during data reception.
The reception conditions
that cause the DVII to
request an interrupt are listed in Table 3-3. The
PDP-II program should respond
to the interrupt
by reading the Receiver Interrupt
Character Reg-
ister to identify the condition and may then load
the Receiver
Control Byte secondary register with
a new control byte. The PDP-II program should
then set
SCR 08. SCR 07 does not cause an inter-
rupt unless SCR 06 has been set to one by the
PDP-II program.
Cleared by Initialize. This bit
is read only except when SCR 09 is set, in which
case
it is read/write.
08 Receiver Interrupt
Set
to one by the PDP-II program when it has com-
Read or Write
Service
Complete
pleted an interrupt service routine and desires
Microprocessor servicing
of the character in the
Receiver Interrupt
Character register. Setting of
this bit clears SCR 07. Cleared by Initialize.
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