User`s manual

The DV 11 provides such a double-register system in
the form of two registers for storage of transmitter
current addresses and two registers for storage of
transmitter byte counts. The registers are called prin-
cipal current address, alternate current address, prin-
cipal byte count, and alternate byte count. Thus,
while the DVi i is transferring data from the table
defined by the principal current address and byte
count, the PDP-II program may establish and load
the alternate current address and byte count. When
the principle byte count reaches zero, the DVII con-
tinues the data transfer operation, without inter-
ruption, by switching to the alternate registers and
notifies the PDP-II program, which may then load
the primary registers. This seesaw activity continues
until both byte counts are zero, at which time trans-
mission stops.
3.1.5.2 Table Size and Location - Any memory loca-
tion, including those with extended address, may be
used and data tables may cross extended address
boundaries. Messages to be transmitted or received
may comprise data tables of up to 16,384 bytes.
3.2 DIRECTLY-ADDRESSABLE REGISTERS
The DV I I contains 10 registers which may be directly
addressed by the PDP-II program. Formats, desig-
nations, addresses and mnemonic codes for these reg-
isters are displayed in Figure 3-3. The System Control
Register (SCR) and the Line Control Register (LCR)
are used by the PDP-II program principally to set up
data transfers. The Control Status Register (CSR)
and the Line Status Register (LSR) are used to set up
the line modems. Other directly-addressable registers
are provided to enable interrupt interpretation and
handling, access to DV II secondary registers, and for
maintenance functions.
The register bit description tables contain a
read/write column to indicate whether bits are read
only, write only, or may be both read and written by
the PDP-II program. If a bit may be physically read
by the program but the datum read is not valid, it is
listed as
"write" with the "only" omitted; the con-
verse case is similarly treated.
3.2.1 System Control Register (SCR)
The System Control Register is a byte-addressable
register for use by the PDP-II program in order to:
I. I nitialize the Data Handling Section of
the DVII Master Clear
3-8
2. Start the DVII Microprocessor
3. Enable DV II data interrupts and detect
interrupt requests
4.
Restart DVII Data Handling Section
after receiver interrupt and
5. Set the extended address bits to the DVII
for core memory addressing by the DVII.
The SCR also provides PDP-II program control of
Microprocessor ROM functions and provides simu-
lated transmission interrupts for maintenance
purposes.
Format of the SCR is displayed in Figure 3-3. Bit
assignments
are described in detail in Table 3-2.
3.2.2 Line Control Register (LCR)
The Line Control Register is intended for use by the
PDP-II program in order to:
I. Enable reception on a selected line
2. Read the extended address bits used for
core memory addressing by DVII second-
ary registers,
and
3. Select the sync character(s) for each line.
The LCR also implements the principal DVII
maintenance functions.
The following LCR bit descriptions apply only to
those lines associated with a synchronous line card.
The enabling of reception is controlled by separate
storage for each line. This is accomplished by using
LCR 15 as a strobe pulse generator to load LCR 13
(Receiver Enable) into control storage for the line set
in
SRS 00-03 at the time that LCR is set to I by the
PDP-II program. The Sync Character Selection bit
(LCR 10) and Maintenance bits LCR 09, II, 12, and
14 are set in separate storages for each four-line
group (00-03, 04-07, 08-11, and 12-15, as selected by
SRS 02-03) by LCR 15 strobe. Consequently, LCR
bits 09-14 are not valid for a line selected at a random
point in time and so are designated as write bits.
Since LCR 15 strobes 09-14, programs must update
all of the bits 09-14 when it is desired to update any
one of these bits. The LCR format for synchronous
line cards is displayed in Figure 3-3. Bit assignments
are described in detail in Table 3-3.