User`s manual
3.1.4.3 Control Byte Inhibit -
For
protocols such as
DDCM
P,
which do
not
require
arbitrary
mode
changes within a
data
block, provision has been
made
to
inhibit the control byte fetch cycle. All characters
are included in BCC,
and
all
are
stored.
The
PDP-II
program
sets the inhibit bit
in
the
Line Protocol
Parameters
secondary register (bit 05 for receive. bit
06 for transmit).
The
inhibit
is
effective only when the
DVll
is
in
mode
O.
If
DDCrvfP
is
implemented with
control tables,
but
the
Control
Byte Inhibit feature is
desired, the control table must provide space for
mode
0, despite
the
fact
that
the
hardware does
not
actually reference
that
part
of
the
table.
3.1.4.4
Sync Character Selection -
Two
sync charac-
ters (A
and
B)
may
be
manually set for each four-line
group
(00-03, 04-07, 08-11, 12-15). Selection
of
the
sync character for a line
is
then accomplished by set-
ting the
Sync
A/B
Selection bit
(LCR
10)
coincident
with the
Control
Strobe
(LCR
15).
The
bit
is
initialized
to
sync A (zero).
3.1.4.5
Sync/Mark
State
Select - The selected sync
character
is
also used as the transmitted Fill charac-
ter. In lieu
of
syncs, the
data
line can be set
to
idle
the
MAR
K state upon hoth byte counts reaching zero by
setting Line Protocol Parameters bit 00
to
I. Idling
of
syncs takes place for a definite
number
of
character
times. Idling
of
the
MARK
state occurs for
an
indeterminate period (Le., synchronization is lost).
3.1.4.6 Stripping Received
Syncs - Setting Line Pro-
tocol Parameters bit
01
to
I causes sync characters
arriving after the achievement
of
synchronization,
but
before the first non-sync character,
to
be stripped
from
the
incoming
data
stream (i.e.,
not
stored
in the
RC
Silo). Sync characters with which
the
receiver
achieves sync
are
stripped in
any
case.
3.1.4.7 Line
Activity Snapshot -
The
PDP-ll
pro-
gram
can
monitor
conditions on a selected line
by
examining bits 00-07
of
the
Line
State
Register,
which provide a
snapshot
of
line activity.
Of
particu-
lar interest
in
Line State
03
(Transmitter
U nderrun).
This
is
set
to
one
by
the
DVII
whenever
data
is
not
available
in
time for the synchronous transmitter,
and
indicates
that
one
or
more idling syncs have been
sent. I n byte count-oriented protocols
or
in
IBM's
3-7
BISYNC transparency operation, idling
of
a sync
causes a
bad
BCC
and
hence a
NAK
from the remote
terminal.
Thus,
the
Transmitter
Underrun
bit
indicates whether the N AK is the result
of
line
errors
or
idling syncs.
3.1.5
Data
Transfer Operations
To
establish a
data
transfer operation between core
memory
and
a selected
data
line for either transmis-
sion
or
reception, the
PDP-II
program
must
commu-
nicate
the
following basic information
to
the
DVII:
a.
The
identification
of
the selected
data
line.
b.
The
quantity
of
data
to
be transferred,
and
c.
the
address
of
the
table
of
locations in
memory (the
"data
table")
for
data
read
or
write.
The
PDP-II
program
specifies
the
selected
data
line
number
in
bits 00-03
of
the SRS.
The
quantity
of
data
to be transferred
is
specified by loading a byte
count
into the
appropriate
DVII
secondary register.
Similarly. the
program
loads the base address
of
the
core memory table into the
DVII
secondary register
provided.
U sing
the
data
table address
to
access the corre-
sponding location in core memory, the
DVII
starts
the
data
transfer. As each byte is transferred, the
DVII
increments
both
the byte
count
and
the
data
table
address
(termed the
"current
address").
When
the byte
count
reaches zero, the
DVII
initiates
data
block
termination
procedure
and
halts
data
reception
for the corresponding line.
(Data
transmission
is
han-
dled
somewhat
differently, as will now be described).
3.1.5.1 Provision for Alternate
Data
Transmission
Tables -
By
means
of
the
data
sequencing
method
just
described,
data
can be transferred between
core
memory
and
the selected
data
line
at
the
maximum
DVII
throughput
rate. However, if
more
than
one
data
table
is
to
be transmitted,
the
program
would
have only
the
transmission time
of
the
last byte
of
the
previous table in which
to
establish a
current
address
and
byte
count
for the next message, unless a double-
register system was provided.