User`s manual
3.1.3.2 Accessing Secondary Registers -
The
Sec-
ondary
Register Selection Register (SRS) provides
for
PDP-II
program
access
to
the secondary registers
in
the
DVII
RAM.
To
address a secondary register,
the PO
P-ll
program
sets the 8-bit
RAM
address,
consisting
of
the 4-bit line number, plus the 4-bit reg-
ister selection code, in SRS 00-03 and SRS 08-11,
respectively. Loading
or
reading the SRS is
then
accomplished by loading
or
reading the Secondary
Register Access Register (SAR).
The
contents
of
the
SRS
must
be saved by interrupt service routines.
3.1.3.3
Data
Transfer Enabling -
The
System Con-
trol Register
(SCR)
provides for clearing the
Data
Handling
Section
(SCR
II)
and
starting the Micro-
processor
(SCR
(0)
to enable the
Data
Handling Sec-
tion. Individual receivers
are
then enabled by setting
the line
number
in bits 00-03
of
the SRS, then setting
Receiver Enable in Line
Control
Register
(LCR
bit
13), coincident with the
Control
Strobe
(LCR
15).
Individual transmitters
are
enabled by setting Trans-
mitter
Go
(bit 02) in the Line State Secondary
Register.
3.1.3.4 Interrupt Enabling and Response -
Data
Handling Section interrupts may occur as a result
of
receive function
interrupt
conditions
or
transmit func-
tion
interrupt
conditions. Receive function interrupts
occur as a result
of
error
conditions, encounter
of
data
block boundaries,
or
upon fetching a control
byte for a received control character
that
specifies an
interrupt. Receive function
interrupt
information is
stored in
the
RIC
register.
Transmit
function interrupts occur as a result
of
error
conditions
or
data
block boundaries being encoun-
tered.
Transmit
functions interrupt information
is
stored
in
a first-in, first-out buffer; the
output
of
this
buffer forms the
NPR
Status Register (NSR). The
buffer
(or
"silo")
is
monitored ot detect overflow.
Receive function interrupts,
transmit
function inter-
rupts,
and
NSR
silo overflow interrupts, when
enabled by
SCR
06,
13,
12,
set
SCR
07,
15, 10,
respectively.
The
PDP-II
program
should
set
SCR
08 in response
to a receiver interrupt, enabling
the
DV
II
to
process
3-6
the character
in
the RIC register and resume with-
drawing characters from the RC Silo.
3.1.3.5 Extended Memory Addressing -
If
the
DVII
is
to
ac~ess
a core memory tables
at
extended memory
locations, the basic 16-bit table address
is
set
in
the
appropriate
secondary register. The extended address
bits are the set
in
SCR
04, 05. The
DVII
appends the
extended address bits to the 16-bit table address and
stores the resultant
I8-bit
in
the SRS (the
RAM
is
18
bits wide).
LC R bits
04,
05
display the extended memory address
bits for the secondary register selected by the
SRS,
for reading by the
PDP-II
program.
3.1.4 Protocol Processing
Processing and control
of
protocol functions is
accomplished almost exclusively with secondary reg-
isters, as indicated in Table 3-1.
3.1.4.1
Bee
Polynomial Selections - The code set in
bits 03, 04
of
the Line Protocol Parameters Second-
ary Register selects the type
of
block check poly-
nomial
to
be applied
to
the transmitted
and
received
data
for error-checking purposes. Longitudinal redu-
ndancy checks (LRC), cyclic redundancy checks
(CRC-16), and
CRC/CCITT
checks are provided
for.
3.1.4.2 Processing Block Terminations - Mode
changes
and
BCC anticipations
or
transmission may
be
effected
at
the end
of
a
data
block
if
the
PDP-II
program
sets a marked byte
count
into a byte
count
secondary register.
The
mode change
and/or
BCC
command
is
then set by
the
PDP-II
program
into the
appropriate
secondary register before
or
during the
data
block receive
or
transmit interval. When the
byte
count
reaches zero, the
"mark"
is
detected by
the
DVll,
which responds
to
the mode change
and/or
BCC
command.
Byte counts are set in 2's complement form in bits
00-14
of
byte
count
secondary registers; the registers
are incremented with each byte transferred
to
count
them
up
to
zero. Thus, a byte
count
may be marked
by setting bit
15
to
zero
at
byte
count
set time. When
the marked byte
count
reaches zero
(00-14=0),
bit
15
is
set
to
one, enabling the
DVII
to detect
the
mark.