User`s manual
....
1_---&.
_______
.L...-_"""'"--_--'--_--L.._---"_x
......... 1 TRANSMIT CONTROL BVTE
07
DISCARD/STORE EXPECT
BCC
X=NOT USED
INCLUDE
CHAR
IN
BCC
00
INTERRUPT
PROGRAM
RECEIVE CONTROL
BYTE
11-2682
Figure 3-2
Control
Byte
Formats
The interrupt disposition provides for signalling
the
program
in
the event
of
error
conditions,
or
data
link
control characters requiring special handling.
The
character
that
caused the interrupt
is
loaded
into
the
RIC
register.
The
program
responds
by
sending a
special control byte
to
the OVI
l,
which would then
override
the
previous dispositions set for received
characters. The
discard disposition provides for
inhibiting storage
of
data
link control
and
other
unwanted characters.
The
do-not-accumulate dis-
position provides for
the
exclusion
of
non-data; BCC
anticipation signals characters from
the
error-check-
ing process. BCC anticipation signals the
DVII
to
initiate
data
block termination procedure.
3.1.2.3 Transmit Control Byte - Whenever a charac-
ter
is
input
to
the
DVII
from
PDP-II
core memory,
the associated control byte
is
obtained
from
core
memory by a
NPR
to
specify
the
next
mode
and
any
other
processing instructions.
The
following instruc-
tions a re provided:
I.
2.
Accumulate
(or
do
not
accumulate)
the
character in
the
BCC.
Send the BCC after
the
character.
3.
Send the D LE before
the
character.
As
in
the case
of
the receive
control
byte,
the
do-not-
accumulate disposition provides for the exclusion
of
non-data
characters from
the
error-checking process.
The
BCC transmission
command
signals the
DVII
to
initiate
data
block termination procedure.
The
DLE
3-5
transmission
command
causes the
OVII
to
retrieve
the
OLE
character
from secondary register storage
and
"stuffs"
the
OLE
in
front
of
the
character
to
be
transmitted.
.1.1.2.4 Control Byte Symmetry - The receive
and
transmit control bytes are configured so
that
a single
control table will provide for both transmit
and
receive functions for a given line
if
the following func-
tional limitations
are
observed:
I.
The protocol must progress from
mode
to
mode in a symmetrical fashion for
both
transmit
and
receive;
2.
the same characters must be included in
the BCC for
both
transmit
and
receive.
For
protocols
that
do
not
meet these requirements,
separate control tables may
be
used.
3.1.3
Operations
With
Directly-Addressable
Registers
The
directly-addressable registers provide
for
modem
setup
and
control
data
transfer enabling,
interrupt
enabling
and
reporting, extended-memory addressing
and
access
to
secondary registers (see
Table
3-1).
3.1.3.1
Modem
Setup
and
Control
-
Modem
enabling. monitoring,
and
control
are
provided
by
the
Control
Status Register
(CSR)
and
the
Line
Stat-
us Register
(LSR)
of
the
Modem
Control
Unit. Step-
by-step procedures for accomplishing these functions
are contained in
Paragraphs
3.5
and
3.6.