User`s manual
3.1.2
Control
Table
The
control
table
contains
the
control
bytes fetched
from
core
memory
by
the
DV
II
each
time
a
character
is
received
or
is
to
be
transmitted.
The
control
bytes
are
used
by
the
DVII
to
control
processing
of
the
transmitted
or
received
character.
3.1.2.1
Control
Table
Format
-
The
addresses
in
core
memory
for
each
line
of
the
receiver
and
trans-
mitter
control
tables
are
set
in
secondary
registers
by
the
PDP-II
program.
The
DV
II
adds
the
character
code
to
the
base
address
to
form
the
basic
core
mem-
ory
address
of
the
control
byte
for
that
character.
For
example,
if
the
base
address
of
the
receiver
control
table
for
a given line
is
4000
and
the
character
101
code
is received
(ASCII
letter
A), 4101
would
be
effective
core
memory
address
of
the
associated
con-
trol
byte.
With
this
scheme, 256
locations
(28)
are
sufficient
to
provide
control
bytes
for every possible 8-bit
charac-
ter
code.
In
the
usual
protocol,
however,
certain
codes
are
susceptible
to
more
than
one
mode
of
inter-
pretation,
depending
upon
the
sequence
in
which
they
are
received
and
whether
the
data
is
transparent
or
non-transparent.
Thus,
3-bit
mode
specification
fields
are
provided
in
secondary
registers for
each
line
in
the
transmitter
and
receiver functions.
Sequencing
between
modes
may
be
effected by
the
control
byte,
which
specifies
the
mode
in which
the
DVII
is
to
operate.
Parameter
EXTENDED
ADDRESS
The
mode
field
occupies
bits 8,
9,
and
10
and
is
appended
to
the
basic
control
table
address
to
form
the
actual
address
of
the
control
byte.
Thus,
in
the
example
above,
the
control
bytes
for
character
code
101
would
be in
location
4101
(mode
0),
location
450 I
(mode
1),
location
5101
(mode
2), etc.
The
con-
trol
byte
address
formation
sequence is
graphically
depicted
in
Figure
3-1.
Control
byte
formats
are
shown
in
Figure
3-2.
3.1.2.2 Receive Control Byte -
Whenever
a
charac-
ter
is
input
to
the
DV
II
from
the
data
link receiver,
the
associated
control
byte
is
obtained
from
core
memory
by a
Non-Processor
Request
(NPR)
to
spec-
ify
the
next
mode
and
to
dictate
character
dis-
position.
The
following
character
dispositions
are
provided:
l.
2.
3.
4.
Generate
(or
do
not
generate)
an
interrupt.
Store
(or
discard)
the
character.
Accumulate
(or
do
not
accumulate)
the
character
in the Block
Check
Character
(BCC).
Expect
the
BCC
(treat
the
next
character
as
a BCC).
BITS
ADDRESS
Table Base Address
Character Code
Mode
No.
Resultant
Address
of
Control Byte
,-----""---v
17 16 15
14
13
12
11
10
09 08
07 06
05
04
03 02
01
00
[~=[
~
I 0 I 0 I 0 I 0
11
I 0 I 0 I 0 I 0 I 0 I 0 I 0 I 0 I 0 I 0 I 0 I
Shifted)
[~I~
1 0 1 0 1 0 1
01
1
1 0
11
1 0 1 0
11
1 0 1 0 1 0 I 0 1 0
11
I
11-2683
Figure
3-1
Control
Byte
Address
3-4