User`s manual

This chapter contains all information required for
controlling operation of the DVII Communications
Multiplexer by means of the PDP-ll program.
(Chapter I should be read prior to this chapter.) The
reader should also be familiar with synchronous pro-
tocols as discussed in Appendix B. Chapter contents
are arranged as follows:
I. Programmable Facilities
and Functions:
The programmable registers, core memo-
ry table references, and functions of the
DVi i are discussed (Section 3.i).
2. Complete, detailed descriptions of pro-
grammable registers and control bytes
(Sections 3.2, 3.3, 3.4).
3. Procedures for DVII initialization (Sec-
tion 3.5).
4. Methods for controlling data transfers
and implementing protocols (Section 3.6).
Section 3.1 describes DV II functions in sufficient
detail to enable the reader to omit a detailed study of
the comprehensive reference data in Sections 3.2, 3.3,
and 3.4, and to proceed directly to the procedural
data in Sections 3.5 and 3.6.
3.1 PROGRAMMABLE FACILITIES AND
FUNCfIONS
The DVII is a core memory-to-synchro-
nous/asynchronous data line multiplexer with special
features to facilitate processing of a wide variety of
communication protocols. Under the overall direc-
tion
of the PDP-II program, the DVII sets up the
data line modems, stores and retrieves data from core
memory, monitors
and reports error conditions, and
examines each transmitted or received character to
3-1
CHAPTER 3
PROGRAMMING
determine and respond to requirements for auxiliary
protocol processing (i.e., block check calculations,
data block terminations, control character handling).
The PDP-II program directs DVII activities through
the programmable registers of the DVII, along with
a control table set up in core memory for reference by
the
DVII.
3.1.1 Programmable Registers
The DV
i i programmable registers consist of the
"primary" system registers. which are directly
addressable via the
Unibus, plus "secondary" regis-
ters, which may be accessed by the PDP-II program
after first loading a primary register. (The primary
register selects the secondary register to be accessed.)
The directly-addressable registers provide for modem
setup
and control, data transfer enabling, interrupt
enabling and reporting, extended memory address-
ing, and access to secondary registers. The secondary
registers provide for protocol processing and data
transfer control.
Ten directly-addressable registers are provided.
There are 16 secondary registers provided for each of
the 16 multiplexed data channels, for a total of 256
secondary registers. The secondary registers make up
a separate Random Access Memory (RAM) within
the DV
II. Secondary registers store functions that
may vary from line to line, and that require the exten-
sive storage capacity
of the RAM.
Functions of programmable registers are described in
Paragraphs 3.2 and 3.3, following a discussion
of the
control table. Functions, functional categories,
and
table references for programmable registers are listed
in Table 3-1, which
is provided for reference during
study of Paragraphs 3.1.3 and 3.1.4.