DV11 communications multiplexer user's manual
EK-OV11-0P-001 DV11 communications multiplexer user's manual digital equipment corporation • maynard, massachusetts
1st Edition, December 1976 Copyright © 1976 by Digital Equipment Corporation The material in this manual is for informational purposes and is subject to change without notice. Digital Equipment Corporation assumes no responsibility for any errors which may appear in this manual. Printed in U.s.A. This document was set on DIGITAL's DECset-8000 computerized typesetting system.
CONTENTS Page CHAPTER 1 INTRODUCTION AND GENERAL DESCRIPTION 1.1 1.2.1 1.2.1.i 1.2.1.2 1.2.2 1.3 1.3.1 PURPOSE AND SCOPE . . . . . . . . . . . . DVII COMMUNICATIONS MULTIPLEXER . DVll Overview Block Diagram Establishing the Data Link DVll Operation . . Reference Documents PHYSICAL DESCRIPTION General Specifications CHAPTER 2 INSTALLAnON 2.1 2.1.1 2.1.2 2.1.3 2.1.4 2.1.4.1 2.1.4.2 2.1.4.3 2.1.5 2.3.1 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.
CONTENTS (Cont) Page 3.1.4.3 3.1.4.4 3.1.4.5 3.1.4.6 3.1.4.7 3.1.5 3.1.5.1 3.1.5.2 3.2 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.2.7 3.2.8 3.2.9 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.7 3.3.8 3.3.9 3.3.10 3.3.11 3.3.12 3.3.13 3.3.14 3.3.15 3.3.16 3.4 3.5 3.5.1 3.5.2 3.6 3.6.1 3.6.2 3.6.3 3.6.4 3.6.4.1 3.6.4.2 3.6.5 3.6.5.1 3.6.5.2 Control Byte Inhibit . . . . . . . . . . . . . . . . . . . . . . Sync Character Selection . . . . . . . . . . . . . . . . . . . Sync/Mark State Select . . . . .. . . . . . . .
CONTENTS (Cont) Page APPENDIX A PDP-II MEMORY ORGANIZATION AND ADDRESSING CONVENTIONS APPENDIX B PROTOCOLS FOR BINARY SYNCHRONOUS COMMUNICATIONS APPENDIX C GLOSSARY OF TERMS AND ABBREvlAnONS ILLUSTRATIONS Figure No.
TABLIS (Cont) Table No. 34 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 TItle Line Control Register Bit ASSignments (For Asynchronous Line Cards) Receive Function Interrupt Conditions (For Synchronous Line Cards) . . . . Receive Function Interrupt Conditions (For Asynchronous Line Cards) Transmit Function Interrupt Conditions . . . . .
CHAPTER 1 INTRODUCTION AND GENERAL DESCRIPTION 1.1 PURPOSE AND SCOPE This manual is intended to provide operational programming information for the DVll Communications Multiplexer. The manual consists of three chapters plus appendices: 8 or 16 serial data lines can be multiplexed directly to PDP-II core memory for bidirectional data transfer.
MODEM CONTROL INTERRUPT MODEM CONTROL UNIT SET-UP DATA LINES TO REMOTE MODEMS MODEMS I ---------------~----DATA HANDLING VI ::l CD Z ::l Q. oQ. SYNC 6FLAGS ...------4 MICRO- ...------f ~------.. PROCESSOR ......----t 8 RECEIVED CHARACTER SILO ~-------"1 RECEIVER INTERRUPT CHARACTER REGISTER ~--------~8~---------------------------------' ~--------~ 8 t--------------------------------------------11- Z896 Figure I-I DVII Overview Block Diagram 1.2.1.
The Received Character (RC) Silo is a first-in, firstout storage buffer with a capacity of 128 characters. When a character is received by the DVII and the RC Silo is empty (usual condition), the character propagates to the bottom of the RC Silo. The Microprocessor then inspects the character code to compute the core memory address of the control byte for that character. A Non-Processor Request (NPR) instruction is issued by the l\tficroprocessor to fetch the control byte, which is then interpreted. 1.2.
Table 1-1 Reference Documents Title Description GENERAL PDP-II Peripherals Handbook Discussion of overall system, addressing modes, and basic instruction set from a programming point of view. Some interface and installation data. PDP-II Instruction List Pocket-size list of instructions. List group names, functions, codes, and bit assignments. Includes ASCII codes and the bootstrap loader.
Figure 1-2 DVII Communications Multiplexer Parity Generation and Detection Odd, Even, or None Sync Character Facility Synchronization of a line can be selected to be on the basis of the receipt of either one sync character or two consecutive, identical sync characters. For each 4-line group, two sync codes may be manually preset in switches. The PD P-II program may select either of those two sync codes for use on a selected line.
CHAPTER 2 INSTALLATION This chapter provides information for interfacing, installing, and testing the DVII Communications Multiplexer. Interfacing considerations are discussed in Section 2.1, Site Preparation and Planning. Installation, customizing, and checkout procedures are discussed in Sections 2.2 through 2.7. 2.1 2.1.2 Compatibility Considerations and Precautions The DVII with synchronous line cards is directly compatible with Bell synchronous modems 201, 208, 209, or equivalent.
DVlls should be connected ahead of all Massbus devices on the Unibus and behind unbuffered NPR devices such as RK05s. DVlls have placement requirements similar to those for DQIls. If both DQ II sand DV II s are used, place the units with the highest baud rate first. If all DVlls have 16 lines at a 9600 baud rate, a maximum of I DVII can be connected with the following exceptions: 2.
Table 2-1 EIA Electrical Specifications Driver output logic levels with 3K to 7K load is V>oh> S V -5 V >01> -15 V Driver output voltage with open circuit IV 0 1< 25 V Driver output impedance with power off 20>300 ohms Output short circuit current dv Driver slew rate dt < 30 Vps Receiver input impedance 7KO> R in > 3KO Receiver input vol tage ± 15 V compatible with driver Receiver output with open circuit input Mark Receiver output with +3 V input Space Receiver output with -3 V input Mar
~.2 UNPACKING AND INSPECfION \fter unpacking, check that the following parts are )resent for the basic DVII-AA unit: 2.3 INSTALLATION OF BASIC ASSEMBLIES Drawing D- UA- DV 11-0-0 shows the physical arrangement of the wired backplane, distribution panel(s) and cables in a typical installation. Figure 2I is the DV 11 interconnection schematic. Install the 9-slot, double system unit in the expander box or processor box as space and power are available.
DVII. Two Unibus addresses (also called device addresses) and two interrupt vector addresses are provided on the D V II as follows: 2.3.1 Unibus Cable Interconnections The DV II is shipped with one M920 Unibus Connector (placed in slot 9 as shown in the module utilization program, Figure 2-2), which provides for electrically connecting the unit to the PDP-II Unibus. For processor box installation where the unit is to be electrically placed in mid-bus (i.e.
1 2 3 4 5 6 7 8 M920 M7836 M7837 M7838 M78391 ~+~~r ~i~~~1 ~~~~~I M7833 CABLE A UNIBUS CONNECTOR NOTE 3 9 M920 CABLE ALU AND TRANSFER BUS UNIBUS DATA AND NPR CONTROL ROM RAM AND BRANCH MUX LINE CARD MUX LINE CARD MUX LINE CARD MUX LI NE CARD UNIBUS CONNECTOR NOTE 1 LINES 0-3 LINES 4-7 LINES 8-11 LINES 12-15 NOTE 2 S B C M7807 M7808 BUS CONTROL AND MUX MODEM CONTROL SCAN AND MUX - 0 E - F VIEW FROM WIRING SIDE NOTES: t. If end of bus replac. M920 with M930. 2.
A12 A11 A10 A09 AOS ON=O OFF = 1 A07 A06 A05 A04 UNUSED 7414-3 Figure 2-3 DVII M7836 Module - Device Address Selection Switches 2-7
7414-1 Figure 2-4 DVll M7837 Module - Interrupt Vector Address Selection Switches for DVll Data Handling Section 2-8
DEVICE ADDRESS (A03 -A12) W18 W12 W17 Jumper W8 W9 Wl0 Wll W12 W13 W14 W15 W16 W16 W17 W13 Bit A12 A09 AOS Al0 A04 A06 A11 A03 A06 A07 Jumper In-O Wl0 Wll W9 W5 INTERRUPT VECTOR ADDRESS (002 -DOS) W8 Jumper Bit DOS 002 003 006 007 005 004 Jumper In = 1 W1 W2 W3 W4 W5 W6 W7 W15 W1 W14 W2 W7 W3 W4 W6 7414-11 Figure 2-5 DVII M7807 Module - Device Address Selection Jumpers and Interrupt Vector Address Selection Jumpers for DVII Modem Control Unit 2-9
Table 2-2 Device Address Switches M7807 Jumper M7836 Switch Address Bit -o IV I W8 I AI2 WI4 2 All X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Wll 3 AIO W9 4 A09 WIO S AOS WI6 6 A07 WI7 7 A06 WI3 8 AOS WI2 9 A04 A03* Device Address Notes 775000 First DV 11 X 775020 775040 First DV 11 MeV Second DVII X 775060 775100 Second DV II MeV Third DVl1 X 775120 775140 Third DVII MeV Fourth DVII X 775160 Fourth DVII MeV X X WIS Note: X means switch off
Table 2-3 Vector Address Switches for Data Handling Section (Vector Addresses are Modulo 10) M7837 Switch Address Bit 1 5 4 D05 D04 6 D03 x X X X X X X X X X X D08 2 D07 3 D06 Vector Address 300 310 X 320 330 X X X X X X 340 350 X 360 370 X X X X X X X X X X X X X X X X X X X X X X X X X X 420 X 430 440 450 X X X X X X X X X X X 500 510 X 520 X 530 540 550 X X X 460 470 X X 400 410 X X X X 560 570 etc. to 770 Notes: 1.
Table 2-4 Vector Address Jumpers for Modem Control Unit (MCU Vector Addresses are Modulo 4) M7807 Jumper Address Bit WI· DOS WS 007 W4 006 W6 DOS W7 004 W3 003 W2 D02 X X X X X X X X X X X X X X X X X X X X X X X X X Vector Address 300 304 X 310 314 X 320 324 X 330 334 X X X X X X X X X X X 340 344 X 350 354 X X X X X X 360 364 X X 370 374 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 40
Table 2-4 (Cont) Vector Address Jumpers for Modem Control Unit (MCU Vector Addresses are Modulo 4) M7807 Jumper Address Bit WI· D08 WS D07 W4 D06 W3 D03 W6 DOS W7 D04 X X X x X X X X X X X X X X X X W2 D02 X Vector Address 510 I 514 520 524 530 534 540 544 550 554 560 564 X X X X X X X X X X X X X X X X X X X ~70 X X 574 X etc. to 774 Notes: 1. X means jumper OUT 2. Cut only the jumpers shown. 3. ·Jumper WI is in for the PDP-I 1/20 with the K.
SWITCH PACK 4 Sync Character A SWITCH PACK 3 Sync Character B 7414-6 SWITCH PACK 2 Baud rate and Duplex Select SWITCH PACK 1 Parity. Character length.
Table 2-5 Synchronous Parameter Selection Switches Switch Function Internal Baud Parameter 1200 Baud Rate 2400 Baud 4800 Baud 9600 Baud Full/Half Full Duplex * Duplex Half Duplex Name Pack Number Select B S2 3 Select A S2 4 ON ~olo"t 0 ~J""",",,\.U S2 "2 ..J f""'\11..
Table 2-5 (Cont) Synchronous Parameter Selection Switches Parameter Function Sync Req. (cont) Sync Character 2 SYNC REO. Desired Code Switch Pack Name Number 1 SYNC 00 SI 5 ON 1 SYNC 01 SI 6 ON 1 SYNC 02 SI 7 ON 1 SYNC 03 Sl 8 ON Sync A S4 1 (As required ,j, OFF=Logi- Codes Desired Code S3 Sync B 8 cal one) 1 (As required ,j, OFF=Logi- 8 cal one) 2.4.
2.5 SYSTEM CHECKOUT Turn on the power. Toggle in the Bootstrap and load the Absolute Loader (if not already done). The addresses and contents of the Bootstrap Loader are listed below. Address l"'f~_~_ •. IVI~IIIVI Y ~:_~ ~IL~ .,,,,, - - - I .... Contents 1\ 1 £ .
D!STR !BUT!ON PANEL EIA CONNECTOR H325 TEST CONNECTOR P. GND EIA XMIT DATA 00 EIA RCV DATA 00 J1-2 - - -.....\ RTS 00 J 1- 3 ------'. CTS 00 J1-4~ J 1-5 S GND CARRIER 00 J1-8 (202 SEC TX gg) NEW - - 1 - - - - - - 0 - - 0 - - . - SYNC W02A 00 ·1 J 1 - 1 1 - - -... J1-i2 - - - - - - ' J1-15~ W06S J1-24 DCE SCT 00 J1-17 W07S -1------0--<>-- DCE SCR 00 J1-20----.. J1-22---~ ( NEW* SYNC ( "A" DTR 00 J1-6---~ RI 00 J 1 - 1 4 - - -.....
CHAPTER 3 PROGRAMMING This chapter contains all information required for controlling operation of the DVII Communications Multiplexer by means of the PDP-ll program. (Chapter I should be read prior to this chapter.) The reader should also be familiar with synchronous protocols as discussed in Appendix B. Chapter contents are arranged as follows: I. determine and respond to requirements for auxiliary protocol processing (i.e., block check calculations, data block terminations, control character handling).
Table 3-1 Functions of DVll Programmable Registers Type Directly Addressable (Modem Control Unit) Directly Addressable (Data Handling Section) Name Control Status Register (CSR) Initialization, Modem Enabling, Modem Scanning, Interrupt Enabling, Interrupt Requests. line Status Register (LSR) Modem Control, Modem Status Reporting Secondary Register Selection (SRS) Secondary Register Selection, Line Selection for line Control Register Bits 9-14. Secondary Reg. Access Reg.
Table 3-1 (Cont) Functions of DVII Programmable Registers Type Indirectly Addressable (Secondary) (Cont) FUllctiOilS Name Transmitter Alternate Current Address Current Address for Tra nsmitter Alternate Data Table Transmitter Alternate Byte Count Byte Count for All ernat e Transmitter Data Table R(~ceiver Current Address for Re(:eiver Data Table Current Address Re~eive:r Receiver Byte Count Byte Count for Transmitter Accumulated BCC Transmitter Accumulat(~d BCC Receiver Accumulated BCC Receiv
The mode field occupies bits 8, 9, and 10 and is appended to the basic control table address to form the actual address of the control byte. Thus, in the example above, the control bytes for character code 101 would be in location 4101 (mode 0), location 450 I (mode 1), location 5101 (mode 2), etc. The control byte address formation sequence is graphically depicted in Figure 3-1. Control byte formats are shown in Figure 3-2. 3.1.
1_---&. . . _______ 1 .L...-_"""'"--_--'--_--L.._---"_x ......... 07 TRANSMIT CONTROL BVTE 00 RECEIVE CONTROL BYTE DISCARD/STORE X=NOT USED EXPECT BCC INCLUDE CHAR IN BCC INTERRUPT PROGRAM 11-2682 Figure 3-2 Control Byte Formats The interrupt disposition provides for signalling the program in the event of error conditions, or data link control characters requiring special handling. The character that caused the interrupt is loaded into the RIC register.
3.1.3.2 Accessing Secondary Registers - The Secondary Register Selection Register (SRS) provides for PDP-II program access to the secondary registers in the DVII RAM. To address a secondary register, the PO P-ll program sets the 8-bit RAM address, consisting of the 4-bit line number, plus the 4-bit register selection code, in SRS 00-03 and SRS 08-11, respectively. Loading or reading the SRS is then accomplished by loading or reading the Secondary Register Access Register (SAR).
3.1.4.3 Control Byte Inhibit - For protocols such as DDCM P, which do not require arbitrary mode changes within a data block, provision has been made to inhibit the control byte fetch cycle. All characters are included in BCC, and all are stored. The PDP-II program sets the inhibit bit in the Line Protocol Parameters secondary register (bit 05 for receive. bit 06 for transmit). The inhibit is effective only when the DVll is in mode O.
The DV 11 provides such a double-register system in the form of two registers for storage of transmitter current addresses and two registers for storage of transmitter byte counts. The registers are called principal current address, alternate current address, principal byte count, and alternate byte count. Thus, while the DVi i is transferring data from the table defined by the principal current address and byte count, the PDP-II program may establish and load the alternate current address and byte count.
SYSTEM CONTROL REGISTER (SCR) 77 5000 15 14 12 13 NPR STATUS INT. 09 10 11 07 08 06 04 05 03 02 00 01 NPR OVFLOW I NT OVFLOW INT. EN. NPR INTERRUPT MASTER ENABLE CLEAR REC.INT RECVR.INT ROM DATA ROM SINGLE SERViCE ENABLE SOURCE STEP COMPLETE BIT 15 RECVR.
SPECIAL FUNCTIONS REGISTER (SFR) 775012 ROM DATA REGISTER CONTENTS '5 I I I\ '4 12 '3 11 R I R NPR STATUS REGISTER (NSR) 775014 10 09 08 07 06 04 05 J\ VALID ENTRY IN 00-" UNUSED R I 1 03 ,[ I NTERRUPT CODE 02 01 R 00 R I I LINE NUMBER UNUSED 11-2690 RESERVED REGISTER (RIR) 775016 07 08 '5 00 x_+----+---_+----~--~----~--_+-x 11-2691 CONTROL STATUS REG ISTER (CSR) 775020 (FOR SYNCHRONOUS LINE CARDS) RING TRANSITION CLEAR TO SEND TRANS CLEAR SCAN DATA SET READY TRANS CA
15 14 LINE STATUS REGISTER (LSR) 775022 (FOR SYNCHRONOUS LINE CARDS) 12 10 08 13 11 09 07 02 01 06 05 04 03 I R I '- I J R R 00 R UNUSED RING CLEAR TO SEND CARRIER ON NEW SYNC DATA SET READY TERMINAL READY REO TO SEND LINE ENABLE MODEM CONTROL MODEM STATUS 11-2693 1 5 LI N E STATUS REGISTER (LSR) 775022 (FOR ASYNCHRONOUS LINE CARDS) , 2 14 1 3 11 10 09 08 07 06 RI N G CLEAR TO SEND CARRIER ON MODEM STATUS SECONDARY RECEIVE REO TO SEND SECONDA RY TRANSMIT LINE ENABLE TERM I N
Table 3-2 System Control Register Bit Assignments Bit(s) 00 Designation Microprocessor GO Function Read/Write When set to one, enables the Microprocessor to operate the DVll Data Handling Section. Must be set to one to enable DVII to perform any functions other than modem control. Cleared by Initialize. Read or Write 01-03 (Maintenance) .
Table 3-2 (Cont) System Control Register Bit Assignments Bit(s) Designation Function Read/Write 09 (Maintenance) 10 NPR Status Overflow (Vector B) Set to one by the Microprocessor whenever the ~..TR Status Register/silo is full. Failure occurs whenever the PDP-II program does not promptly read the NPR Status Register contents following a SCR 15 interrupt, and 64 NPR status entries have occurred. SCR 10 does not cause an interrupt unless SCR 12 has been set to one by the PDP-II program.
Table 3-3 Line Control Register Bit Assignments (For Synchronous Line Cards) Bit(s) 00-01 02-03 04-05 06 07-09 10 Designation Function Read/Write (Maintenance) - Extended Address Read - - Unused For the secondary register selected by SRS 00-03 and 08-11, these bits display the contents of bits 16 and 17, respectively. This enables the program to read the extended address bits of the current address and control table base address secondary registers.
Table 3-3 (Cont) Line Control Register Bit Assignments (For Synchronous Line Cards) Bit(s) 15 Function Designation Control Strobe When set to one, strobes LCR 13 into control storage for the line set in SRS 00-03 and strobes LCR 09, 10, 11, 12, 14 into control storage for the 4-line group set in SRS 02-03, then clears itself. May be set at the same time as the LCR bits that it strobes into storage for the selected line or line group. Read/Write Write The format of the RIC is shown in Figure 3-3.
Table 3-4 Line Control Register Bit Assignments (For Asynchronous Line Cards) Bit(s) 00,01 02,03 04,05 06,07,08 Designation Function Read/Write (Maintenance) - Extended Address Read - - Unused - For the secondary register selected by SRS 00-03 and 08-11, these bits display the contents of bits 16 and 17, respectively. This enables the program to read the extended address bits of the current address and control table base address secondary registers.
Table 3-4 (Cont) Line Control Register Bit Assignments (For Asynchronous Line Cards) Bit(s) Function Designation Read/Write Asynchronous Line Card Primary Register 09,10 Primary Register Selection Code 00 For the line number selected by SRS 00-03, the code of 00 specifies writing into the Primary register at LCR 15 set time. Write 11 Half Duplex! Full Duplex This bit, when set, conditions the line to operate in half duplex mode.
Table 3-4 (Cont) Line Control Register Bit Assignments (F or Asynchronous Line Cards) Bit(s) Function Designation Read/Write Asynchronous Line Card Format Register 09,10 Format Register Selection Code 10 For the line number selected by SRS 00-03, the code of 10 specifies writing into the Format register at LCR 15 set time. LCR 09 = 1, LCR 10 =O. Write 11,12 Character Length These bits are set to transmit and receive characters of the length (excluding parity) as shown below.
Table 3-4 (Cont) Line Control Register Bit Assignments (For Asynchronous Line Cards) Bit(s) Read/Write Function Designation Asynchronous Line Card Baud Rate Register (Cont) 14 11-14 (Cont) 12 0 0 1 1 0 0 1 1 0 0 1 1 0 0 13 o o o o o o o o 0 0 0 0 1 0 1 o o o II Baud Rate 0 .)V 1 0 1 0 1 0 1 0 1 0 1 0 1 0 rn 75 110 134.
Table 3-4 (Cont) Une Control Reg~ter Bit Assignments (For Asynchronous Line Cards) Bit(s) Designation Function Read/Write Asynchronous Line Card Maintenance Register 09,10 Maintenance Register Selection Code 11 For the line number specified by SRS 00-03, the code of 11 specifies writing into the Maintenance register at LCR 15 set time. Write 11 Maintenance Internal Mode This bit, when set, loops the transmitter's serial output lead to the receiver's serial input lead.
Table 3-S Receive Function Interrupt Conditions (For Synchronous Line Cards) Code Set in RIC 12-IS IS 0 I 14 0 I 13 0 I 12 0 Meaning Special Character Received: Bit 00 of the control byte for the character in RIC 00-07 is set to one (gentft .... t" .. ttftft .1."" •• "'.,,,,, •• n ••• "'u ... Ar",t.,. tfttA .... nt \ ".u,"'" • 0 0 0 0 0 0 0 .I.1ft .,",,,,t ."A ."'1"'0.".0,1 ,...J.-ft.",,,,,tA •• L" ",a,ul. ...." .I"""'''''''''''' ""IIGIU""""" .I" .... a ra",A"".",,1 " ...........
Table 3-5 (Cont) Receive Function Interrupt Conditions (For Synchronous Line Cards) Code Set in RIC 12-15 15 14 13 12 1 1 1 0 Processing Error 10: The DV 11 received a signal on the memory parity error line from the PDP-II when the DVII attempted to store the character set in RIC 00-07. This con dition indicates a defect in the memory parity logic, as the PDP-II generates parity error signals only on core memory read operations.
Table 3-6 (Cont) Receive Function Interrupt Conditions (For Asynchronous Line Cards) Code Set in RIC 12-1 5 IS 14 13 I 12 Meaning o Undefined o Undefined o o o o o o Byte Count Zero: The receive byte count for this line was zero prior to receipt of the character set in RIC 00-07. Thus, the character was not stored as no assigned storage was available.
Table 3-7 Transmit Function Interrupt Conditions Code Set in NSR OS-II Meaning Transmiiter principal current address specified a non-existent memory location (NXM). a a a a a 0 a a Transmitter principal byte count is equal to zero. a Transmitter alternate current address specified a non-existent memory location (NXM). Transmitter alternate byte count is equal to zero. 0 0 An attempted control byte fetch by the DVII produced a non-existent memory condition or a memory parity error.
Table 3-8 Control Status Register Bit Assignments Bit(s) Designation 00-03 LINE (Line Number) Read/Write Function Binary address of one of 16 modems: Bit o 3 2 n v n v n v o o o n v Read or Write Line No. n v 15 Cleared to 0000 by Initialize or Clr Scan (bit 11 of CSR). Sixteen microseconds ±IO% settling time is required.
Table 3-8 (Cont) Control Status Register Bit A~ignments Bit(s) Designation Function Read/Write 07 DONE Set to one whenever a transition occurs on a status line (RING, CO, CS, DSR) from an enabled modem during the modem scanning process, as initiated by Scan En (CSR bit 5). When Done is set to one, the scan stops and the status transition(s) are se.t in CSR bits 12-15.
Table 3-8 (Cont) Control Status Register Bit Assignments Bit(s) Designation Function Read/Write 12 DSR (Data Set Ready transition) (Synchronous modem definition) Set to 1 whenever an ON to OFF or OFF to ON transition occurs on the DSR status line from the selected modem. Not valid if the PDP-II program has changed the line number in CSR bits 0-3 and the scan has not been cycled for one or more lines by Scan En (CSR bit 5) or Step (CSR bit 8). Cleared by Initialize or Clr Scan.
Table 3-9 Line Status Register Bit Assignments Bit Designation Function Read/Write 00 LINE EN (Line Modem Enable) When set to 1 for the line selected by bits 0-3 of the CSR, causes status conditions DSR, CS, CO, and RING from the corresponding modem to appear in bits 4-7 of the LSR and causes status transitions from the same modem to set the Done bit (CSR bit 7) to 1 during the scanning process.
Table 3-9 (Cont) Line Status Register Bit Assignments Designation Bit 06 CO (Carrier On) (detected) 07 RING Function Read/Write Set to 1 whenever the CO line from the modem selected by bits 0-3 of the CSR is ON, provided that the Line En bit for that modem is present and that the received signal is present for demodulation. Read only Set to 1 whenever the RING line from the modem selected by bits 0-3 of the CSR is ON, provided that the Line En bit for that modem has been set.
TRANSMITTER PRINCIPAL CURRENT ADDRESS (0000) 15 00 TRANSMITTER PRINCIPAL BYTE COUNT (0001) 15 00 1 - NORMAL BYTE COUNT 0· MARKED BYTE COUNT TRANSMITTER ALTERNATE CURRENT ADDRESS (0010) 15 00 TRANSMITTER ALTERNATE BYTE COUNT (0011) 15 00 , = NORMAL BYTE COUNT 0=MARKED BYTE COUNT RECEIVER CURRENT ADDRESS (0100) 15 00 RECEIVER BYTE COUNT (0100 15 00 ,S NORMAL BYTE COUNT 0- MARKED BYTE COUNT TRANSMITTER ACCUMULATED BLOCK CHECK CHARACTER (0110) 15 00 RECEIVER ACCUMULATED BLOCK CHECK CHARACT
TRANSMITTER CONTROL TABLE BASE ADDRESS (1000) 15 00 RECEIVER CONTROL TABLE BASE ADDRESS (10011 15 00 LINE PROTOCOL PARAMETERS (1010) 15 OB 07 06 05 04 03 02 00 01 IDLE MARK ON BOTH B.C.:/a LINE STATE (1011) 14 15 12 09 10 l' 08 07 06 05 04 02 03 01 00 NEXT RCV. MODE ON MARKED BYTE COUNT:" USE ALTERNATE TABLES TRANSMITTER MEMORY PARITY ERROR 7"~~~.. Sf;..
3.3.3 Transmitter Alternate Current Address (0010) The Transmitter Alternate Current Address register has exactly the same function as the Transmitter Principal Current Address register described in Paragraph 3.3.1. This register is incremented by one with each character transmitted by the DVII on the associated line if the alternate message table is being used (Line State secondary register bit 07 set to one).
3.3.9 Transmitter Control Table Base Address (1000) The Transmitter Control Table Base Address secondary register contains the 18-bit address of the transmitter control table for the associated line. The extended address bits are initially ioaded from SCR 04-05 to provide the 18-bit address capability. The contents of this register are used by the Microprocessor in the computation of the control byte addresses for transmitted characters.
Table 3-10 Line Protocol Parameters Secondary Register Bit Assignments Bit(s) Designation Function Read/Write 00 Idle Mark When set to one, causes the associated data line to go to the MARK state at the conclusion of transmission of the character currently being loaded into the transmitter if both principal and alternate byte counts are zero. When cleared, sync characters will be idled on a :synchronous data line or a MARK STATE will be asserted on an asynchronous line.
Table 3-11 Line State Secondary Register Bit Assignments Bit(s) Designation Function Read/Write . 00 Receiver Active Set to one by the Microprocessor when the enabled receiver for the associated line has detected the synchronization character(s) for that iine. (Receiver enabling, done via the Line Control Register, is discussed in Paragraph 3.2.2.
Table 3-11 (Cont) Line State Secondary Register Bit Assignments Bit(s) Designation Function Read/Write 04 Transmitter NonExisten t Memory (NXM) Set to one by the Microprocessor whenever a nonexistent memory condition is encountered during transmission (NPR Status Register interrupt codes 0000,0010,1000). The PDP-II program should read the NPR Status Register, then clear this bit. This bit clears Transmitter Go (Line State 02) when set to one.
Table 3-11 (Cont) Line State Secondary Register Bit Assignments Bit(s) Designation 11-12 13-15 Function Read/Write When a marked receiver byte count reaches zero; the Microprocessor transfers these bits to bits 00-02 of the Receiver Mode Bits secondary register to set the mode for the next character(s) to be received.
Table 3-12 (Cont) Line Progress Secondary Register Bit Assignments Bit(s) 05 Designation Expect BCCI Function (Not intended for access by the PDP-II program.) Set to one by the Microprocessor whenever (1) Line State bit II (Expect BCC) has been set to one by the PDP-II program and a marked byte count has reached zero, or (2) a receive control byte has been fetched with bit 03 (Expect BCC) set to one.
Table 3-12 (Cont) Line Progress Secondary Register Bit Assignments Bit( s) 07 Designation Resynchronization Rag Expected Read/Write (Not intended [or access by the PDP-II program.) Set to one by the Microprocessor whenever a resynchronization cycle starts for the associated line receiver as commanded by Line State 01. Oeared by the Microprocessor when all characters stored in the RC Silo for the associated line have been removed.
Table 3-13 Control Byte Bit Assignments Function Bit(s) Receiver Control Byte Transmitter Control Byte 00 Unused (to effect symmetry) Interrupt PDP-II Program: When set to one, causes the DVII to request a PDP-II program interrupt. The DVII sets the received character being processed in the Receiver Interrupt Character Register and awaits a reset of SCR 08 by the PDP-II program.
3.5 DVll INITIALIZATION DV II initialization consists of setting up the DVII line modems and the DVII Data Transfer Section. LCR 10 and 13 are implemented for synchronous reception on a line. When operating on an asynchronous line, character format and baud rate must be set up at this time. 3.5.1 Line Modem Set-Up I nitialization for the line modems consists of setting the line number for the modem to be enabled in CSR 00-03.
3.6.1 Originating and Answering Calls The Control Status Register (CSR) arid the Line Status Register (lSR) are provided to enable the PDP-II program to originate and answer calls to/from remote modems. Initially, the local modem is enabled and the operating mode (interrupt or non-interrupt) is set, as described in Paragraph 3.5.1. An interchange then takes place between the PDP-II program and the MCU to originate a call, as follows: 1.
3.6.4 BISYNC Implementation BISYNC implementation software is considered in three functional groups: control tables, interrupt service routines, and the protocol module. be loaded with the base addresses and byte counts for data buffers one and two, respectively. On each zero byte count interrupt, the next buffer address would be loaded into the appropriate registers. The control tables contain the control bytes, which control sequencing between modes and accumulation of the BCC.
NONTRANSPARENT TRANSPARENT o 3 INITIAL TRANSPARENT TRANSMISSION INITIAL NONTRANSPARENT TRANSMISSION 4 NONTRANSPARENT TEXT TRANS- TRANSPARENT DATA TRANSMISSION YES 2 END OF TRANSPARENT BLOCK 11-2949 Figure 3-5 BISYNC Transmission Flow Diagram 3-44
Table 3-14 Transparent Data Transmission Control Control Byte Directives Stuf Send BCC After A DLE? This Character? Data Buffer No. Contents o STX 2 3 4 - Current INCL. CHAR. IN BCC? YES YES CHAR. 1 CHAR. N** 1 (2)* - - YES ITB DLE STX 2 2 2 - YES YES - - - 1 - - YES YES YES CHAR. 1 1 - - - YES CHAR. N** 1 (2)* - - YES - u .. ,.'r .. YtS -YcS -- _~~_ w • __ . . - _ 1:1 Xj1:1 H ~ 2 **If Char.
o WAITING FOR MESSAGE NO TRANSITION TO TRANSPARENT RECEPTION YES 2 3 TRANSPARENT DATA RECEPTION NONTRANSPARENT DATA RECEPTION 4 TRANSPARENT CONTROL CHARACTER YES ·RECEIVED THE BCC 11-2950 Figure 3-6 BISYNC Reception Flow Diagram 3-46
Mode 1 (Transition to Transparent Reception) I n this mode, the system initializes for the reception of transparent text. Mode I is entered only from Mode 0 following reception of a OLE. An STX is expected; if one is received, it is discarded (an interrupt is generated to set the Transparent Data flag). and Mode 3 is set. generated, the buffer contents are turned over to the protocol module, and address and byte counts are set to receive the 2-byte BCC.
3.6.5.2 Reception Control - Figure 3-8 is a flow chart for the DDCMP reception process. Initially, the DV II receive registers are set to receive the six bytes of the incoming DDCMP header and bit 15 of the byte count register is cleared to direct reception of the BCe. 1. SET PRlt"CIPAL XMIT REGS WITH HEADER BUFFER AD· DRESS & B.C. The first character in the first buffer is now examined to determine message type.
A y SET TO RECEIVE DV'T"~~ oJ U I Ir;..~ eIDCT., "'lUI - - DV11 INTERRUPT SET TO RECEIVE SECOND 3 BYTES BOOTSTRAP (DLEI OR DATA (SOHI CONTROL (ENOl DV11 INTERRUPT GET CHARACTER COUNT AND BUILD RECEIVE BUFFER - CHECK BCC - DV11 INTERRUPT RETURN 1. CHECK HEADER BCC 2.
APPENDIX A PDP-II lVlElVlORY ORGANIZATION .~ND A.DDRESSING CONVENTIONS The PDP-II memory is organized into 16-bit words consisting of two 8-bit bytes. Each byte is addressable and has its own address location: low bytes are evennumbered, high bytes are odd-numbered. Words are addressed at even-numbered locations only and the high (odd) byte of a word is automatically included to provide a 16-bit word. Consecutive words are therefore found in even-numbered addresses.
~ 08107 16 BIT DATA WORD HIGH BYTE 00000 1 000003 ~ LOW BYTE r---------~------~ ---- 000000 000002 -- 757777 757776 760001 760000 -*777777 - 1 USER ADDRESS SPACE AVAILABLE USING 18 ADDRESS BITS ON PDP-11 PROCESSOR WITH MEMORY MANAGEMENT OPTION. INCLUDES 248K(253,952) BYTES OR 124K(126,976) WORDS. -- HIGHEST 8K (8192) BYTES OR 4K(4096) WORDS RESERVED FOR DEVICE REGISTER ADDRESSES. 777776 J LLAST ADDRESS IS BYTE NUMBER 262.
HIGH BYTE LOW BYTE 000001 000000 1 000003 000002 I USER ADDRESS SPACE I :g~~~:~:~~::i~~6 I I ~ ' I 157777 157776 160001 160000 -*'77777 WITHOUT MEMORY MANAGEMENT OPTION. INCLUDES 56K (57, 344) BYTES OR 28K (28,672) WORDS. ADDRESSES 160000177777 ARE CONVERTED TO 760000 -777777 BY THE PROCESSOR. THUS, THEY BECOME THE HIGHEST 8K (8192) BYTES OR 4K( 4096) WORDS RESERVED FOR DEVICE REGISTER ADDRESSES. --..
APPENDIX B PROTOCOLS FOR BINARY SYNCHRONOUS COMMUNICA.TIONS data terminal is capable of transmitting a fixed number of bits per second in each direction; the control bits reduce the effective rate of information transfer. The ratio of the information bits to the total bits determines the one-way line utilization efficiency. The more control, header and error-checking characters needed by a protocol, the less efficient the line.
B.2 DATA AND CONTROL CODES The purpose of a data channel is to transfer data, unaltered, from a transmitter station (master) to a receiver station (slave). The data to be transferred is embedded in control codes, which serve to identify the type of data being transferred, and to provide for synchronization and error detection. (Thus, the channel is considered to consist of the physical facility plus control codes.
Bit Position P 6 5 4 3 2 01aracter 1 0 Character 2 0 0 0 0 0 0 0 Character 3 0 0 0 0 0 Character 4 0 0 0 0 0 LRC-8 BCC 0 0 0 0 Figure B-1 Polling and addressing on multipoint lines are handled by a separate control message and not by using the header field. The text portion of the field is variable in length and may contain transparent data. If it is defined as transparent, it is delimited by DLE (Data Line Escape) STX and DLE ET (End of Text), or DLE ETB (End of Text Block).
control character to be recognized as a control function. When a bit pattern equivalent to DLE appears within the transparent data, two DLEs are used to permit transmission of DLE as data. When received, one DLE is disregarded; the other is treated as data. This technique is called "character stuffing." Table B-1 BSC Data Channel Control Codes Control Code Mnemonic SYN Meaning Synchronous Idle B.3.
BB SOH COUNT FLAG 14 BITS 2BITS RESPONSE SEQUENCE 8 BITS 8 BITS ADDRESS CRC-1 8 BITS 16 BITS DATA (ANY NUMBER OF 8-BIT CHARACTERS UP TO 214 ) CRC-2 16 BITS 11-2897 Figure B-4 DDCMP Data Message Format Figure B-5 shows a simple example of data exchange between the D V III PD P-II and a data terminal. More efficient procedures can be derived after a study of DDCMP. B.4.2 Error Checking and Recovery DDCMP uses CRC-16 for detecting transmIssIon errors.
TERMINAL DVII/PDP-Il Sends a STRT (START) message which means: "I want to begin sending data to you and the !i:equence numher of my first message will be 1."_ _ _ _ _ _ -----""(2) ____0 \....J 0) CD Receives STRT message. Sends a STACK (Start Ac!c'1ow!edge) message which means: "OK with me; here is the first sequence number (5) I will use in sending data messages to you." Receives STACK. Sends Data Messages with a response field set to 4 and the sequence field set to I.
B.4.6 Synchronization OOCM P achieves synchronization through the use of two ASCII SYN characters preceding the SOH, ENQ, or OLE. It is not necessary to synchronize between messages as long as no gap exists. Gaps are filled with SYN characters. Two sync characters are required, but more are usually transmitted. If synchronization between messages is deliberately lost by sending PA 0 (all I s) characters, the intermessage interval must be at least 14 character times in length. B.4.
APPENDIX C GLOSSARY OF TERMS AND ABBREVIATIONS A CK - Acknowledgment ACK O. ACK I (Affirmative Acknowledgment) - These replies (DLE sequence in Binary Synchronous Communications) indicate that the previous transmission block is accepted by the receiver and that it is ready to accept the next block of the transmission. Use of ACK 0 and ACK I alternately provides sequential checking control for a series of replies.
Concentrator - A communications device that provides a communications capability between many low-speed, usually asynchronous channels, and one or more high-speed, usually synchronous channels. Usually different speeds, codes, and protocols can be accommodated on the low-speed side. The low-speed channels usually operate in contention, requiring buffering. The concentrator may have the capability to be polled by a computer, and may in turn poll terminals.
EBCDIC - Extended Binary Coded-Decimal Interchange Code. An 8-bit character code used primarily in I BM equipment. The code provides for 256 different bit patterns. Echo - A portion of the transmitted signal returned from the distant point to the source with sufficient magnitude and delay so as to cause interference. ENQ (Enquiry) - (a.) Used in BISYNC as a request for response to obtain identification and/or an indication of station status.
lYon-Processor Request (N PR) - High priority data transfers to the PDP-II Processor. These are direct memory access type transfers, and are honored by the processor between bus cycles of an instruction execution. NPR data transfers can be made between any two peripheral devices without the supervision of the processor. N ormaHy, N PR transfers are between a mass storage device, such as a disk and core memory.
Synchronous Idle (S Y N) - Character used as a time fill in the absence of any data or control character to maintain synchronization. The sequence of two continuous SYNs is used to establish synchronization (character phase) following each line turnaround. entry to and exit from the transparent mode is indicated by a sequence beginning with a special Data Link Escape (OLE) character.
Reader's Commen DVll COMMUNICATIONS MULTIPLEXER USER'S MANUAL EK-DVII-OP-OOI Your comments and suggestions will help us in our continuous effort to improve the quality and usefulness { our publications. What is your general reaction to this manual? In your judgment is it complete, accurate, well organized, well written, etc.
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