Specifications

Software Interface 35
Table 3–1 (Cont.) CSR Bit Assignments
Bits Name Function
13:08 Memory bank
(MB)
MB is a read-write field. The MB field provides the
bank selection bits (21 through 16) to the module
memory address decoder. For example, suppose the
memory bank field is set to 12
16
and the memory
enable bit is set. In this case, the module responds
to Q-bus memory references for locations 120000
16
through 12FFFF
16
.
The addressing of the module memory is
programmable. The MB field is cleared when the
Q-bus is initialized (BINIT) or when the module is
powered up.
14 Timer interrupt
enable (TI)
TI is a read-write bit. TI is intended for real-time
applications that run the module using a polling
scheme.
The interval timer is a free-running clock with
a host-programmable rate. By default, the timer
rate is set to 125 microseconds. Soft-loaded module
firmware can change the rate.
The timer generates an interrupt whenever the
timer sends a clock signal while the TI bit is
set. The module automatically clears the timer
interrupt after it sends the interrupt to the host.
The TI bit is cleared when the Q-bus is initialized
(BINIT) or when the module is powered up.
15 Module alert
(MA)
MA is a read-write bit. Writing a 1 to the MA bit
sets it. Writing a 0 to MA has no effect. Setting
MA requests a module alert interrupt. The module
clears MA after it acknowledges the alert interrupt.
The MA bit is cleared when the Q-bus is initialized
(BINIT) or when the module is powered up.
The host sets or clears the MA bit according to
certain guidelines. Basically, the host must set the
MA bit to alert the module that the host has moved
data into the module’s shared memory. For details
on the DECvoice interrupt scheme, see Section
3.3.2.1