Specifications

34 Software Interface
Table 3–1 (Cont.) CSR Bit Assignments
Bits Name Function
05 Memory enable
(ME)
ME is a read-write bit. When ME is set, the Q-bus
can access the module memory. When ME is reset,
the Q-bus cannot access the module memory. The
ME bit is cleared when the Q-bus is initialized
(BINIT) or when the module is powered up.
NOTE
The ME bit prevents all the DECvoice
modules in a system from responding to
memory location 0 at power-up. This makes it
possible to control several DECvoice modules
using a single 64 Kbyte area in Q-bus address
space.
06 Alert interrupt
enable (AI)
AI is a read-write bit. An alert interrupt occurs in
one of two cases:
• The host alert bit is set while the AI bit is set.
• The AI bit is set while the host alert bit is set.
Generally, the host must acknowledge any alert
interrupt by explicitly clearing the host alert bit.
The AI bit is cleared when the Q-bus is initialized
(BINIT) or when the module is powered up.
07 Host alert (HA) HA is a read-write bit. The module sets HA to
request a host alert interrupt. The host must clear
HA to acknowledge the request. Writinga1tothe
HA bit clears it. Writinga0totheHAbithasno
effect. The HA bit is cleared when the Q-bus is
initialized (BINIT) or when the module is powered
up.
The module sets or clears this bit according to
certain guidelines. Basically, the module sets the
HA bit to alert the host that data movement has
occurred in the module’s shared memory. For
details on the DECvoice interrupt scheme, see
Section 3.3.2.1