Specifications

Software Interface 33
NOTE
DECvoice treats all write cycles to the CSR as complete word
cycles. DECvoice does not support the writing of individual bytes
to the CSR.
Figure 3-1 shows the CSR. Table 3-1 describes the bit assignments in the
CSR.
MA-0555-88
Figure 3–1 The Q-bus Control and Status Register
Table 3–1 CSR Bit Assignments
Bits Name Function
03:00 Module state
(MS)
This field passes the complete module state from
the main microprocessor microcode to the host.
When the main reset bit is set, this field is set to 0.
The microcode determines all other settings of this
field. Table 3-2 lists the settings that the MS field
can have.
04 Main reset (MR) MR is a read-write bit. When MR is set, the main
microprocessor and most other components on the
module are held in the reset state. When MR is
reset, the module restarts. The MR bit is cleared
when the Q-bus is initialized (BINIT) or when the
module is powered up.
NOTE
The MR bit must be asserted for at least
500 nanoseconds to ensure that the reset
operation is complete.