User`s guide

4.2 21164 Address Mapping to PCI Space
2. Bits <20:1> of the map entry (PTE) are used to generate the physical
page address. This address is appended to the page offset to generate the
physical memory address. The TLB is also updated with the four PTE
entries that correspond to the 32KB PCI page address, which first missed
the TLB. The tag portion of the TLB is loaded with this PCI page address,
and the DAC bit is set if the PCI cycle was a DAC cycle.
3. If the requested PTE is marked invalid (bit 0 clear), then a TLB invalid
entry exception is taken.
The 21171 chipset provides support for PC compatibility addressing and holes
via PCI bus signal MEMCS#. This allows certain ISA devices to respond to
hardwired memory addresses. For more information, refer to the DECchip
21171 Core Logic Chipset Technical Reference Manual.
System Address Mapping 4–27