User`s guide

4.2 21164 Address Mapping to PCI Space

An 8-entry translation-lookaside buffer (TLB) is provided in the CIA chip for

scatter-gather map entries. The TLB is a fully associative cache and holds

the eight most recent scatter-gather map lookups. Four of these entries can

be ‘‘locked,’’ thus preventing their displacement by the hardware TLB-miss

handler. Each of the eight TLB entries holds a PCI address for the tag, and

four consecutive 8KB CPU page addresses as the TLB data.

Each time an incoming PCI address hits in a PCI target window that has

scatter-gather enabled, bits <30:15> of the PCI address are compared with the

32KB PCI page address in the TLB tag. If a match is found, the required CPU

page address is one of the four data entries of the matching TLB entry. PCI

address bits <15:13> select the correct 8KB CPU page entry from the four.

If no match is found in the TLB, the scatter-gather map lookup is performed

and four page table entries (PTEs) are fetched and written over an existing

entry in the TLB. The TLB entry replaced is determined by a round-robin

algorithm on the ‘‘unlocked’’ entries. TLB coherency is the responsibility of

software by writing to the SG_TBIA invalidate CSR.

The tag portion of the TLB also contains a DAC ﬂag to indicate that the PCI

tag address corresponds to a 64-bit DAC address. Refer to the DECchip 21171

Core Logic Chipset Technical Reference Manual for more information.

The process for a scatter-gather TLB hit is as follows:

1. The window compare logic determines if the PCI address has hit in one of

the four windows. The PCI_BASE<SG> bit determines if the scatter-gather

path should be taken. If window three has DAC mode enabled, and the

PCI cycle is a DAC cycle, then further comparisons are made. Refer to the

DECchip 21171 Core Logic Chipset Technical Reference Manual for more

information on DAC mode.

2. PCI address bits <31:13> are sent to the TLB tag comparator. If the

address and DAC bits match in the TLB, then the corresponding CPU 8KB

page address is read from the TLB. If this entry is valid, then a TLB hit

has occurred and the page address is concatenated with PCI address bits

<12:2> to form the physical memory address. If the data entry is invalid,

or if the tag compare failed, then a TLB miss has occurred.

The process for a scatter-gather TLB miss is as follows:

1. The relevant bits of the PCI address (as determined by the window mask

form the address used to access the scatter-gather map entry from a table

located in system memory.

4–26 System Address Mapping