User`s guide

4.2 21164 Address Mapping to PCI Space
Table 4–10 EB164 Primary PCI IDSEL Mapping
IDSEL Device PCI Address Bit Physical Address
PCI slot 2 pci_ad<16> 87.0005.0000
PCI slot 0 pci_ad<17> 87.0006.0000
PCI slot 1 pci_ad<18> 87.0007.0000
PCI-to-ISA SIO bridge pci_ad<19> 87.0008.0000
PCI slot 3 pci_ad<20> 87.0009.0000
4.2.7 PCI Interrupt Acknowledge/Special Cycle Space (87.2000.0000
Through 87.3FFF.FFFF)
The special cycle command provides a simple message broadcasting mechanism
on the PCI. In general, it can be used for logical sideband signaling between
PCI agents.
The special cycle command contains no explicit destination address, but
is broadcast to all agents. The EB164 drives all zeros as the special cycle
address. Each receiving agent must determine if the message contained in the
data field is applicable to it.
A write access to the CIA chip’s IAC_SC CSR causes a special cycle on the PCI.
The 21164’s write data is passed unmodified to the PCI. Software must write
the data in longword zero of the hexword with the following field:
• Bytes 0 and 1 contain the encoded message.
• Bytes 2 and 3 are message dependent (optional).
A read of the IACK_SC CSR results in an interrupt acknowledge cycle on the
PCI and the return data will be the interrupt vector.
4.2.8 EB164 Hardware-Specific and Miscellaneous Register Space
(87.4000.0000 Through 87.6FFF.FFFF)
This address space is a hardware-specific variant of the sparse space encoding.
CPU address bits <27:6> specify a longword address where CPU address<5:0>
must be zero. All the CIA chip registers are accessed with a longword
granularity. Table 4–11 lists each region and the associated addresses.
For more specific details on the CIA chip’s CSRs, refer to Section A.6 and the
DECchip 21171 Core Logic Chipset Technical Reference Manual.
System Address Mapping 4–19