User`s guide

4.2 21164 Address Mapping to PCI Space
Table 4–8 PCI Configuration Space Byte-Enable Generation
Length
1
CPU addr_h<6:5> CPU addr_h<4:3>
PCI Byte-
Enable
2
pci_ad<1:0>
Byte 00 00 1110 CFG<1:0>
01 00 1101 CFG<1:0>
10 00 1011 CFG<1:0>
11 00 0111 CFG<1:0>
Word 00 01 1100 CFG<1:0>
01 01 1001 CFG<1:0>
10 01 0011 CFG<1:0>
Tribyte 00 10 1000 CFG<1:0>
01 10 0001 CFG<1:0>
Longword 00 11 0000 CFG<1:0>
Quadword 11 11 0000 CFG<1:0>
1
Missing entries produce UNPREDICTABLE results.
2
Byte-enable set to 0 indicates that byte lane carries meaningful data.
Caution
If a quadword access is specified for the configuration cycle, then the
least significant bit (LSB) of the register number field (PCI_AD<2>)
must be zero (MBZ). Quadword accesses must access quadword-aligned
registers.
Table 4–9 shows the EB164 CPU address encoding for PCI device selection.
System Address Mapping 4–17