User`s guide

4.2 21164 Address Mapping to PCI Space
4.2.5 PCI Dense Memory Space (86.0000.0000 Through 86.FFFF.FFFF)
PCI dense memory space is typically used for PCI data buffers (such as a video
frame buffer) and has the following characteristics:
• There is one-to-one mapping between CPU addresses and PCI addresses.
A longword address from the CPU maps to a longword address on the PCI.
Hence, the name dense space (as opposed to PCI sparse memory space).
• Byte or word accesses are not permitted in this space. Minimum access
granularity is a longword on write operations and a quadword on read
operations. The maximum transfer length is 32 bytes on write operations
(performed as a burst of 8 longwords on the PCI) and on read operations.
Any combination of longwords may be valid on write operations. Valid
longwords surrounding an invalid longword (or longwords), called a hole,
are required to be handled correctly by all PCI devices.
• The 21164 cannot specify a longword address for read transactions. The
minimum granularity it can specify is a quadword in noncacheable space.
Therefore, minimum granularity read operations in this space should
always be executed as a quadword read operation with a burst length of
two on the PCI bus. The 21164 merges noncached read operations up to
a 32-byte maximum. The largest dense space read operation is therefore
32 bytes. This space cannot be used for devices that have read side effects
due to load-merging and prefetching operations. Any prefetched data is not
cached between transactions. The burst read on the PCI bus is not atomic.
• Write operations to addresses in this space can be buffered in the 21164.
The EB164 supports a burst length of eight on the PCI, corresponding to
32 bytes of data. In addition, the CIA chip provides four 32-byte write
buffers to increase I/O write performance. These four buffers are strictly
ordered.
The address generation in dense space is as follows:
• CPU address bits <31:5> are directly sent out on PCI address<31:5>.
• CPU address bits <4:3> are generated from the 21164’s int4_valid_h
signals.
• On read transactions, PCI address bit <2> is always 0.
• On write transactions, PCI address bit <2> is generated from the
int4_valid_h signals. If the lower longword is to be written, PCI address
bit <2> = 0. If the lower longword is masked out and the upper longword is
to be written, PCI address bit <2> = 1.
• PCI address bits <1:0> are forced to 0.
System Address Mapping 4–13