User`s guide

4.2 21164 Address Mapping to PCI Space
Table 4–6 PCI Sparse I/O Space Byte-Enable Generation
Length
1
CPU Address
<6:5>
CPU Address
<4:3>
PCI Byte-
Enable
2
PCI Address <2:0>
Byte 00 00 1110 pci_ad<7>,00
01 00 1101 pci_ad<7>,01
10 00 1011 pci_ad<7>,10
11 00 0111 pci_ad<7>,11
Word 00 01 1100 pci_ad<7>,00
01 01 1001 pci_ad<7>,01
10 01 0011 pci_ad<7>,10
Tribyte 00 10 1000 pci_ad<7>,00
01 10 0001 pci_ad<7>,01
Longword 00 11 0000 pci_ad<7>,00
Quadword 11 11 0000 000
1
Missing entries produce UNPREDICTABLE results.
2
Byte-enable set to 0 indicates that byte lane carries meaningful data.
Caution
Quadword accesses to PCI sparse I/O space will cause a two-longword
burst on the PCI bus. Some PCI devices might not support bursting in
I/O space.
Figure 4–4 and Figure 4–5 illustrate the PCI sparse I/O space translation for
each region.
System Address Mapping 4–11