User`s guide

4.2 21164 Address Mapping to PCI Space
to address a 32MB region that can be relocated by using the HAE_IO register
located in the CIA chip.
4.2.4 PCI Sparse I/O Space (85.8000.0000 Through 85.FFFF.FFFF)
PCI sparse I/O space is sparse and has characteristics similar to the PCI
sparse memory space. This 2GB physical address space maps to two 32MB
regions of PCI I/O address space. A read or write operation to this space causes
a PCI I/O read or PCI I/O write command, respectively.
The address generation is as follows:
• Region A: This region has CPU address bits <34:30> = 10110 and addresses
the lower 32MB of PCI sparse I/O space. Therefore, PCI address bits
<31:25> are set to zero by the hardware. This region is used for ISA
addressing.
• Region B: This region has CPU address bits <34:30> = 10111 and addresses
32MB of PCI sparse I/O space that can be relocated. This 32MB segment
is relocated by assigning HAE_IO<31:25> to PCI address<31:25>.
• PCI address bits <24:3> are derived from CPU address bits <29:8>.
• PCI address bits <2:0> are defined in Table 4–6.
The lower 64KB of PCI sparse I/O space should be reserved for the ISA devices.
Therefore, all PCI devices should be relocated above this region.
4–10 System Address Mapping