User`s guide

B–1 Write Cycle Timing ................................ B–6
B–2 Special Header Content . . ........................... B–9
Tables
1–1 Main Memory Sizes ................................ 1–3
2–1 Configuration Jumper Position Descriptions . . . .......... 2–4
2–2 EB164 Connector Descriptions ........................ 2–10
3–1 Bcache Configurations . . . ........................... 3–3
3–2 EB164 System Interrupts ........................... 3–13
3–3 PCI-to-ISA SIO Bridge Interrupts . . ................... 3–15
4–1 Three Physical Memory Regions . . . ................... 4–2
4–2 Physical Memory Regions (Detailed) ................... 4–3
4–3 PCI Sparse Memory Space Byte-Enable Generation ....... 4–7
4–4 INT4_VALID to Address Translation for Sparse Write
Operations . . . ................................... 4–7
4–5 High-Order Sparse Space Bits ........................ 4–8
4–6 PCI Sparse I/O Space Byte-Enable Generation . .......... 4–11
4–7 PCI Configuration Space Definition . ................... 4–16
4–8 PCI Configuration Space Byte-Enable Generation ......... 4–17
4–9 CPU Address Encoding for PCI Device Selection .......... 4–18
4–10 EB164 Primary PCI IDSEL Mapping .................. 4–19
4–11 Hardware-Specific Register Space . . ................... 4–20
4–12 PCI Target Window Enables ......................... 4–21
4–13 PCI Target Address Translation—Direct Mapped (SG
Mapping Disabled) ................................ 4–23
4–14 Scatter-Gather Map Address ......................... 4–24
5–1 Power Supply dc Current Requirements ................ 5–1
5–2 Board Component List . . . ........................... 5–4
A–1 PC87312 Combination Controller Register Address Space
Map............................................ A–2
A–2 Keyboard and Mouse Controller Addresses .............. A–6
A–3 Time-of-Year Clock Device Addresses ................... A–7
A–4 Flash ROM Segment Select Register ................... A–7
A–5 Configuration Jumpers (CONF4—CONF15) . . . .......... A–8
A–6 Interrupt Control PLD Addresses . . ................... A–8
A–7 SIO PCI-to-ISA Bridge Operating Register Address Space
Map............................................ A–9
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