User`s guide

4.2 21164 Address Mapping to PCI Space
Figure 4–2 PCI Sparse Memory Space Address Translation—Region 2
CPU Address
<4:3> Generated from INT4_VALID
0 0
Length in Bytes
Byte Offset
HAE_MEM CSR
PCI Address
1
39
31 27 26 2 1 0
31
MK−2306−06
15 11
34 31 7654321033 32
SBZ 0 PCI Quadword Address10
Figure 4–3 PCI Sparse Memory Space Address Translation—Region 3
CPU Address
<4:3> Generated from INT4_VALID
0 0
Length in Bytes
Byte Offset
HAE_MEM CSR
PCI Address
1
39
31
31
MK−2306−07
34 30 7654321033 32 31
SBZ 0 PCI Quadword Address101
72
26 25 2 1 0
4.2.3 Hardware Extension Registers (HAE)
In sparse space, CPU address bits <7:3> are wasted on encoding byte-enables,
size, and the low-order PCI address bit <2>. Therefore, there are five fewer
address bits available to generate the PCI physical address. Hardware
extension registers (HAEs) are used to provide the missing high-order bits.
The HAE registers are expected to be set by firmware.
The EB164 provides three sparse space PCI memory regions and allows each
to be relocated by means of bits in the HAE_MEM register located in the CIA
chip. Two regions of PCI I/O sparse space are provided, region A and region B.
Region A addresses the lower 32MB of PCI I/O space and is never relocated.
This region is intended to be used to address ISA devices. Region B is used
System Address Mapping 4–9