User`s guide

4.2 21164 Address Mapping to PCI Space
PCI address bits <31:26> are obtained from either the hardware extension
register (HAE_MEM), or the CPU address, depending upon the sparse space
being accessed. This is shown in Table 4–5. HAE_MEM is a CSR in the CIA
chip and is described in Section A.6.1.
Table 4–5 High-Order Sparse Space Bits
PCI Address Bit Region 1 Region 2 Region 3
PCI_AD<31> HAE_MEM<31> HAE_MEM<15> HAE_MEM<7>
PCI_AD<30> HAE_MEM<30> HAE_MEM<14> HAE_MEM<6>
PCI_AD<29> HAE_MEM<29> HAE_MEM<13> HAE_MEM<5>
PCI_AD<28> addr<33> HAE_MEM<12> HAE_MEM<4>
PCI_AD<27> addr<32> HAE_MEM<11> HAE_MEM<3>
PCI_AD<26> addr<31> addr<31> HAE_MEM<2>
Figure 4–1, Figure 4–2, and Figure 4–3 illustrate the PCI sparse memory space
translation for each region.
Figure 4–1 PCI Sparse Memory Space Address Translation—Region 1
CPU Address
<4:3> Generated from INT4_VALID
0 0
Length in Bytes
Byte Offset
HAE_MEM CSR
PCI Address
1 SBZ 0 PCI Quadword Address
39 34 33 7 6 5 4 3 2 1 0
31 29 28 2 1 0
31 29
MK−2306−05
4–8 System Address Mapping