User`s guide

4.2 21164 Address Mapping to PCI Space
Table 4–3 PCI Sparse Memory Space Byte-Enable Generation
Length
1
CPU Address
<6:5>
CPU Address
<4:3>
PCI Byte-
Enable
2
PCI Address
<2:0>
3
Byte 00 00 1110 pci_ad<7>,00
01 00 1101 pci_ad<7>,00
10 00 1011 pci_ad<7>,00
11 00 0111 pci_ad<7>,00
Word 00 01 1100 pci_ad<7>,00
01 01 1001 pci_ad<7>,00
10 01 0011 pci_ad<7>,00
Tribyte 00 10 1000 pci_ad<7>,00
01 10 0001 pci_ad<7>,00
Longword 00 11 0000 pci_ad<7>,00
Quadword 11 11 0000 000
1
Missing entries have UNPREDICTABLE results.
2
Byte-enable set to 0 indicates that byte lane carries meaningful data.
3
In PCI sparse memory space, PCI address bits <1:0> are always 00.
Table 4–4 INT4_VALID to Address Translation for Sparse Write Operations
21164 Data Cycle
1
int4_valid<3:0> CPU Address <4:3>
First 0001 00
First 0010 00
First 0100 01
First 1000 01
Second 0001 10
Second 0010 10
Second 0100 11
Second 1000 11
Second 1100 (STQ)
2
11
1
Missing entries have UNPREDICTABLE results.
2
Only one valid STQ case is allowed.
System Address Mapping 4–7