User`s guide

4.2 21164 Address Mapping to PCI Space
• Software must use longword load or store instructions (LDL/STL) to
perform a reference that is of longword length (or less) on the PCI. The
bytes to be transferred must be positioned within the longword in the
correct byte lanes as indicated by the PCI byte enables. The EB164
performs no byte shifting within the longword. Quadword load and
store instructions must only be used to perform a quadword transfer.
Use of STQ/LDQ instructions for any other references will produce
UNPREDICTABLE results.
• The EB164 does not prefetch in sparse space (no side effects).
• Accesses in this space are no greater than one quadword. Software
must ensure that the processor does not merge consecutive read or write
transactions by using memory barrier (MB) instructions after each read or
write transaction in this address space. However, consecutive sparse space
addresses (that is, to a different PCI longword/quadword) will be separated
by at least 32 bytes and are not merged by the EB164.
• Software must insert MB instructions if the sparse space address can alias
to a dense space address. Otherwise, ordering and coherency cannot be
maintained.
• The encoding of the 21164 address for sparse space read accesses to PCI
space is shown in Table 4–3. It is important to note that CPU address
bits <33:5> are directly available from the 21164 pins. On read operations,
address bits <4:3> can be calculated from the INT4_VALID pins. CPU
address bits <2:0> are required to be zero.
• The relationship between INT4_VALID and CPU address bits <4:3> for
sparse space write operations is shown in Table 4–4.
Table 4–3 defines the low-order PCI sparse memory address bytes. CPU
address bits <7:3> are used to generate the length of the PCI transaction in
bytes, the byte-enables, and address bits <2:0>. CPU address bits <30:8>
correspond to the quadword PCI address and are sent out on PCI address
<25:3>.
4–6 System Address Mapping