User`s guide

4.2 21164 Address Mapping to PCI Space
4.2.1 Cacheable Memory Space (00.0000.0000 Through 00.3FFF.FFFF)
The EB164 recognizes the first 1GB of the physical address space to be
cacheable memory space. It responds to all read and write accesses in this
space. The block size is fixed at 64 bytes.
The EB164 uses a read/flush-based cache coherence protocol. All DMA read
accesses are sent to the 21164 as read probes while all DMA write accesses are
sent to the 21164 as flush probes. DMA read operations that hit in any of the
caches will cause data to be returned from that cache. DMA read operations
that miss all of the caches cause data to be returned from memory. DMA write
operations that hit in any of the caches will cause the entry to be flushed
(invalidated), and if dirty, the data will be merged with the DMA write data
before being written to memory.
4.2.2 PCI Sparse Memory Space (80.0000.0000 Through 85.7FFF.FFFF)
The EB164 provides three regions of contiguous CPU address space that
maps to PCI sparse memory space. Accesses to this space can have
byte, word, tribyte, longword, or quadword granularity, which the PCI
requires, even though the Alpha architecture does not provide byte, word,
or tribyte granularity. In addition, Intel processors are capable of generating
UNALIGNED references, and it is desirable to emulate the resulting PCI
transactions to ensure compatibility with PCI devices designed for Intel
platforms.
Therefore, to provide this granularity, the byte enable and byte length
information is encoded in the lower address bits in this space. Address
bits <6:3> are used for this purpose. Bits <31:7> are used to generate longword
addresses on the PCI bus, thus resulting in a sparse 4GB space that maps to
128MB of address space on the PCI. An access to this space causes a memory
read or memory write access on the PCI.
The rules for accessing this region are as follows:
• Sparse space supports all the byte encodings that can be generated in an
Intel platform to ensure compatibility with PCI device drivers. The results
of some references are not explicitly defined. The EB164 completes the
reference UNPREDICTABLY but does not report an error.
3
3
The CIA chip generates an interrupt if it is enabled in the CIA_ERROR_MASK
register.
System Address Mapping 4–5