User`s guide
4.1 Physical Memory Regions
Caution
Due to CIA chip pin constraints, CPU address bits <38:35> are not
brought onchip. Software must ensure that CPU address bits <38:35>
are always zero (to ensure even parity). Otherwise, the CIA chip will
generate parity error interrupts during address cycles.
4.2 21164 Address Mapping to PCI Space
The control, I/O interface, and address chip (CIA) generates 32-bit PCI
addresses but accepts both 64-bit address (DAC
1
) cycles and 32-bit PCI
address (SAC
2
) cycles. However, the EB164 only supports up to a maximum
of 512MB of main memory, which precludes any benefit from the CIA chip
accepting 64-bit DAC addressing.
The EB164 provides 4GB of PCI dense space to map the complete PCI memory
space. PCI sparse memory space of 704MB is provided, which has byte
granularity and is the safest memory space to use with respect to merging and
prefetching. EB164 provides three PCI sparse memory regions that can be
relocated by means of the HAE_MEM CSR as follows:
• 512MB region that can be located in any NATURALLY ALIGNED 512MB
segment of the PCI memory space. This region might be sufficient for
software needs and the remaining two regions could be ignored.
• 128MB regions that can be located on any NATURALLY ALIGNED 128MB
segment of the PCI memory space.
• 64MB region that can be located on any NATURALLY ALIGNED 128MB
segment of the PCI memory space. This range is intended to be located in
the PCI address segment 0–64MB for ISA space accesses. However, the
region can be relocated for software convenience.
The EB164 provides 64MB of PCI sparse I/O space. PCI devices will probably
not exceed 64KB in the near future, thus 64MB should provide ample space.
The PCI I/O sparse space is divided into two 32MB regions. Region A is
fixed in PCI segment 0–32MB. Region B can be relocated to any 32MB region
through use of the HAE_IO register.
1
Dual-address cycle—used only if address bits <63:32> are non-zero.
2
Single-address cycle—used for 32-bit PCI addresses, or if bits <63:32> are zero for a
64-bit address.
4–4 System Address Mapping