User`s guide

4.1 Physical Memory Regions
Table 4–2 Physical Memory Regions (Detailed)
Region
16
Description
00.0000.0000–00.3FFF.FFFF Cacheable memory space (1GB)
00.4000.0000–7F.FFFF.FFFF UNDEFINED space (511GB)
80.0000.0000–83.FFFF.FFFF PCI sparse memory space—region 0 (16GB through
512MB)
84.0000.0000–84.FFFF.FFFF PCI sparse memory space—region 1 (4GB through
128MB)
85.0000.0000–85.7FFF.FFFF PCI sparse memory space—region 2 (2GB through
64MB)
85.8000.0000–85.BFFF.FFFF PCI sparse I/O space—region A (1GB through
32MB)
85.C000.0000–85.FFFF.FFFF PCI sparse I/O space—region B (1GB through
32MB)
86.0000.0000–86.FFFF.FFFF PCI dense memory space (4GB)
87.0000.0000–87.1FFF.FFFF PCI configuration space (512MB)
87.2000.0000–87.3FFF.FFFF PCI interrupt acknowledge/special cycle space
(512MB)
87.4000.0000–87.4FFF.FFFF CIA main CSR space (256MB)
87.5000.0000–87.5FFF.FFFF CIA memory control CSR space (256MB)
87.6000.0000–87.6FFF.FFFF CIA PCI address translation (256MB)
87.7000.0000–FF.FFEF.FFFF UNDEFINED space (~482GB)
FF.FFF0.0000–FF.FFFF.FFFF Cbox IPR space (1MB)
The EB164 uses a flush-based cache coherence protocol. All DMA read
operation requests are serviced by the 21164 if the data resides in its caches.
Otherwise, data will be returned from memory. All DMA write operation
requests will invalidate matching addresses in the 21164’s caches and, if the
cache entry was dirty, will be merged with the DMA write data before being
written to memory. One exception to this occurs when a DMA locked read
operation is performed; the EB164 will treat the read operation like a DMA
write operation except that the only data that will be written to memory is
cache data if it is dirty. This is done to clear the lock flag in the 21164 and to
flush out the locked block from its caches. All read misses from the 21164 that
subsequently match the locked address will be stalled until the PCI lock is
relinquished. This prevents the 21164 from gaining access to the locked block.
System Address Mapping 4–3