User`s guide

A I/O Space Address Maps
A.1 PCI Sparse Memory Space . . . ........................... A–1
A.2 PCI Sparse I/O Space .................................. A–1
A.2.1 PCI Sparse I/O Space—Region A . . . ................... A–2
A.2.1.1 PC87312 Combination Controller Register Address
Space ........................................ A–2
A.2.1.2 8242AH Keyboard and Mouse Controller Addresses . . . . A–6
A.2.1.3 Time-of-Year (TOY) Clock Addresses ................ A–6
A.2.1.4 Flash ROM Segment Select Register ................ A–7
A.2.1.5 Configuration Jumpers (CONF4—CONF15) .......... A–8
A.2.1.6 Interrupt Control PLD Addresses .................. A–8
A.2.2 PCI Sparse I/O Space—Region B . . . ................... A–8
A.3 PCI Dense Memory Space . . . ........................... A–13
A.3.1 Flash ROM Memory Addresses ....................... A–13
A.3.2 Map of Flash ROM Memory .......................... A–13
A.3.3 Flash ROM Configuration Registers. ................... A–14
A.4 PCI Configuration Address Space ........................ A–16
A.4.1 SIO PCI-to-ISA Bridge Configuration Address Space ....... A–16
A.5 PCI Interrupt Acknowledge/Special Cycle Address Space ...... A–18
A.6 Hardware-Specific and Miscellaneous Register Space ......... A–18
A.6.1 CIA Main CSR Space ............................... A–18
A.6.2 CIA Memory Control CSR Space . . . ................... A–19
A.6.3 CIA PCI Address Translation Map Space................ A–20
A.7 21164 Alpha Microprocessor Cbox IPR Space................ A–22
B SROM Initialization
B.1 SROM Initialization ................................... B–1
B.2 Firmware Interface ................................... B–2
B.3 Automatic CPU Speed Detection ......................... B–4
B.4 CPU Bus Interface Timing . . . ........................... B–4
B.5 Bcache Read and Write Timing Calculations ................ B–6
B.5.1 Read Cycle Calculation . . ........................... B–6
B.5.2 Write Cycle Calculations . ........................... B–6
B.5.3 Read/Write Spacing Calculations . . . ................... B–8
B.6 Memory Initialization ................................. B–8
B.7 Bcache Initialization .................................. B–8
B.8 Special ROM Header .................................. B–9
B.9 Flash ROM Structure.................................. B–12
B.10 Flash ROM Access . ................................... B–15
B.11 Icache Flush Code . ................................... B–16
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