User`s guide

3.6 Interrupts

This section describes the EB164 interrupt logic. PCI-, ISA-, and

CIA-generated interrupts are each described. Figure 3–4 shows the interrupt

logic.

The PCI-to-ISA SIO bridge chip provides the functionality of two 8259

interrupt control devices. These ISA-compatible interrupt controllers are

cascaded such that 14 external and two internal interrupts are available. The

PCI interrupt acknowledge command should be used to read the interrupt

request vector from the SIO.

However, the EB164 has more interrupt signals than the 14 external interrupts

the SIO can handle. Therefore, all the ISA interrupts are sent to the SIO

except for the two CIA interrupts, the time-of-year (TOY) interrupt, and the

16 PCI interrupts. They are sent to an external interrupt PAL. This PAL

takes these interrupts, as well as an OR of the nonexistent memory (NMI)

and error signals from the SIO, and generates cpu_irq<3:0>. During reset,

cpu_irq<3:0> convey the system clocking ratios and delays, which are set by

jumpers on J1.

Table 3–2 lists each system interrupt, its ﬁxed interrupt priority level (IPL),

and its EB164 implementation. Table 3–3 lists each SIO interrupt and its

EB164 implementation.

Table 3–2 EB164 System Interrupts

21164 Interrupt IPL

Suggested Usage EB164 Usage

cpu_irq<0> 20 Corrected system

error

Corrected ECC error and

sparse space reserved

encodings detected by CIA

cpu_irq<1> 21 — PCI and ISA interrupts

cpu_irq<2> 22 Interprocessor and

timer interrupts

Time-of-year clock interrupt

cpu_irq<3> 23 — Reserved

pwr_fail_irq 30 Powerfail interrupt Reserved

sys_mch_chk_irq 31 System machine

check interrupt

SIO NMI and CIA errors

mch_hlt_irq — Halt Reserved

IPL = interrupt priority level (ﬁxed)

Functional Description 3–13