User`s guide

3.3 Main Memory Interface
• 2MB 36-bit DRAM SIMM
• 4MB 36-bit DRAM SIMM
• 8MB 36-bit DRAM SIMM
• 16MB 36-bit DRAM SIMM
The following memory sizes are supported with one set of eight SIMMs:
• 32MB memory
• 64MB memory
• 128MB memory
• 256MB memory
• 512MB memory
The row and column addresses for the DRAM SIMMs are partitioned such that
any victim’s row address will match its corresponding read miss’s row address.
This allows a page-mode-write operation to follow a read operation during read
miss/victim processing.
3.4 PCI Devices
The EB164 uses the PCI bus as the main I/O bus for the majority of peripheral
functions. The board implements the ISA bus as an expansion bus for system
support functions and relatively slow peripheral devices.
The PCI bus supports multiplexed, burst mode, read and write transfers.
It supports synchronous operation of between 25 MHz and 33 MHz. It also
supports either a 32-bit or 64-bit data path with 32-bit device support in
the 64-bit configuration. Depending upon the configuration and operating
frequencies, the PCI bus supports anywhere between 100MB/s (25 MHz, 32-bit)
to 264MB/s (33 MHz, 64-bit) peak throughput. The PCI provides parity on
address and data cycles. Three physical address spaces are supported:
1. 32-bit memory space
2. 32-bit I/O space
3. 256-byte-per-agent configuration space
The bridge from the 21164 system bus to the 64-bit PCI bus is provided by the
CIA chip. It generates the required 32-bit PCI address for 21164 I/O accesses
directed to the PCI. It also accepts 64-bit double address cycles and 32-bit
single address cycles. However, the 64-bit address support is subject to some
constraints. Refer to Chapter 4 for more information on these constraints.
Functional Description 3–7