User`s guide

3.2 Digital Semiconductor 21171 Chipset
Figure 3–2 Main Memory Interface
data<127:0>
Data Switch
(X 4)
Control, I/O Interface,
Main Memory Array
DRAM0 DRAM1 DRAM2 DRAM3 DRAM4 DRAM5 DRAM6 DRAM7
mem_dat<143:0> mem_dat<287:144>
addr_bus_req adr_cmd_par cack cmd<3:0> dack fill fill_error fill_id idle_bc int4_valid<3:0> sys_res<1:0> tag_ctl_par tag_dirty victim_pending
cmc<8:0> ioc<<6:0> mem_en
iod<63:0> iod_ecc<7:0>
mem_addr<11:0>
sense_dis
(7−0)_mem_addr<11:0>
Buffer Buffer
RAS
PLAs
21164
MK−2306−20
eb164.2
eb164.10−.13
eb164.8
eb164.15,16
eb164.17 eb164.17
eb164.18 eb164.19
data_check<15:0> addr<39,34:4> System Control* *
mem_we_h<1:0> cas_h<3:0> set_sel_h<1:0> ras_h<1:0>
mem_we<7:0>_l cas_l<7:0> (1,0)_ras_l<3:0> (1,0)_ras_l<7:4>
and Address
64−Bit PCI
I/O Bus
Functional Description 3–5