User`s guide

3.2 Digital Semiconductor 21171 Chipset

The 21171 chipset provides a cost-competitive solution for designers using the

21164 microprocessor to develop uniprocessor systems. The chipset provides a

256-bit memory interface and a peripheral component interconnect (PCI) I/O

interface, and includes the following two gate arrays:

• 21171-CA control, I/O interface, and address (CIA) chip packaged in a

383-pin, pin grid array (PGA)

• 21171-BA data switch (DSW) chip packaged in a 208-pin plastic quad ﬂat

pack (PQFP)

Figure 3–2 shows the EB164 implementation of the 21171 chipset.

3.2.1 CIA Chip Overview

The control, I/O interface, and addressing (CIA) application-speciﬁc integrated

circuit (ASIC) accepts addresses and commands from the 21164 and drives the

main memory array with the address, and control signals. It also provides an

interface to the 64-bit PCI I/O bus.

The CIA chip provides the following functions:

• Serves as the interface between the 21164, main memory (addressing and

control), and the PCI bus. A 3-entry CPU instruction queue is implemented

to capture commands should the memory or I/O port be busy.

• Provides the DSW chips with control information to direct the data ﬂow.

• Provides the interface to the PCI bus, and therefore, contains a portion of

the data path. This includes the error correction code (ECC) generation

and check logic for data transfers to and from the DSW chips. It also

contains data buffers for all four transaction types (I/O read and write

operations, and direct memory access (DMA) read and write operations).

Each buffer is 64 bytes in size.

• Generates the row and column addresses for the dynamic random-access

memory (DRAM) SIMMs, as well as all the memory control signals (RAS,

CAS, WE). All the required DRAM refresh control is contained in the CIA.

• Provides all the logic to map 21164 noncacheable addresses to PCI address

space, as well as all the translation logic to map PCI DMA addresses to

system memory.

3–4 Functional Description