User`s guide

3.1 EB164 Bcache Interface
The Bcache interface supports multiple cache sizes and access times. The
cache sizes supported are:
• 2MB with Alpha cache single inline memory modules (SIMMs) populated
with 128K 8 static RAMs (SRAMs)
• 2MB, 4MB, and 8MB with SIMMs populated with 512K 8 SRAMs
SRAM speeds of 6 ns to 15 ns can be used. In most cases, wave pipelining can
decrease the cache loop times by one CPU cycle. Performance trade-offs for
each application can then be made between size, speed, and Bcache expense.
Because of the support for smaller Bcache sizes, larger cache sizes contain
extra tag bits. EB164 modules fitted with large caches can be configured
to operate in any of the smaller cache sizes because the extra tag bits are
available. Caches fitted with 512K 8 SRAM SIMMs support all the cache
sizes. Caches fitted with 128K 8 SRAM SIMMs only support the 2MB
configuration. Table 3–1 lists the three supported Bcache configurations.
Table 3–1 Bcache Configurations
Cache Size Block Size Index Tag Control Data ECC
8MB 64-byte <22:4> <29:23>,P V,D,P <127:0> <15:0>
4MB 64-byte <21:4> <29:22>,P V,D,P <127:0> <15:0>
2MB 64-byte <20:4> <29:21>,P V,D,P <127:0> <15:0>
Key to control bits
V = Valid
D = Dirty
P = Parity
The EB164 Bcache operates only in 64-byte mode because the data switch
(DSW) chip only supports 64-byte transfers to and from memory. Wave
pipelined accesses to the Bcache are supported.
Buffers are required between the 21164 and the Bcache SRAMs on the output-
enable and write-enable signals for the data and tags. These buffers provide
the required inversion for the enable signals as well as the load buffering to
drive the multiple SRAMs.
Functional Description 3–3