User`s guide

1.1 System Components and Features
1.1.1 Digital Semiconductor 21171 Core Logic Chipset
The 21164 is supported by the 21171 chipset. The chipset consists of the
following two application-specific integrated circuit (ASIC) types:
• One copy of the 21171-CA control, I/O interface, and address chip (CIA)
provides the interface between the 21164, main memory (addressing and
control), and the peripheral component interconnect (PCI) bus. It also
provides the data switch companion chips with control information to direct
the data flow.
• Four copies of the 21171-BA data switch chip (DSW) provide the memory
interface data path and route PCI data through the CIA chip.
The chipset includes the majority of functions required to develop a high-
performance PC or workstation, requiring minimum discrete logic on the
module. It provides flexible and generic functions to allow its use in a wide
range of systems.
1.1.2 Memory Subsystem
The dynamic random-access memory (DRAM) provides 32MB to 512MB with
a 256-bit data bus. The memory is contained in one bank of eight commodity
single inline memory modules (SIMMs). Single- or double-sided SIMMs may
be used. Each SIMM is 36 bits wide, with 32 data bits and 4 check bits,
with 70 ns or less access. Table 1–1 lists the SIMM sizes supported and the
corresponding main memory size for 256-bit arrays.
Table 1–1 Main Memory Sizes
SIMM Size Eight SIMMs (256-Bit Array)
1M 36 32MB
2M 36 64MB
4M 36 128MB
8M 36 256MB
16M
36 512MB
1.1.3 L3 Bcache Subsystem Overview
The board-level external L3 backup cache (Bcache) subsystem supports
multiple cache sizes and access times. Cache sizes supported are 2MB with
Alpha cache SIMMs populated with 128K 8 SRAMs, and 4MB and 8MB
with SIMMs populated with 512K 8 SRAMs. Speeds of 6 ns to 15 ns can
be used. Wave pipelining decreases the cache loop times by one CPU cycle in
Introduction to the EB164 1–3