User`s guide

RAS
Row address strobe.
region
One of four areas in physical memory space based on the two most significant,
implemented, physical address bits.
RISC
Reduced instruction set computing. A computing system architecture with
an instruction set that is paired down and reduced in complexity so that
most instructions can be performed in a single processor cycle. High-level
compilers synthesize the more complex, least frequently used instructions by
breaking them down into simpler instructions. This approach allows the RISC
architecture to implement a small, hardware-assisted instruction set, thus
eliminating the need for microcode.
Scache
Secondary cache. A 96KB L2 cache reserved for instructions and data on the
21164 chip.
SCSI
Small computer system interface. An interface standard for peripheral devices
such as hard disk drives, CD–ROM drives, and tape drives. The drive contains
most of the controller circuitry, leaving the SCSI interface free to communicate
with other peripherals.
SIMM
Single inline memory module.
SRAM
Static random-access memory.
SROM
Serial read-only memory.
UART
Universal asynchronous receiver–transmitter.
word
Two contiguous bytes (16 bits) starting on an arbitrary byte boundary. The bits
are numbered from right to left, 0 through 15.
Glossary–4