User`s guide

cache for data, and one unified 96KB L2 combined instruction and data cache.
See also Bcache and write-back cache.
CAS
Column address strobe.
CIA
Control, I/O interface, and address chip. Part of the 21171 chipset.
CMOS
Complementary metal-oxide semiconductor.
Dcache
Data cache. An 8KB L1 cache reserved for data on the 21164 chip.
DRAM
Dynamic random-access memory. Read/write memory that must be refreshed
(read from or written to) periodically to maintain the storage of information.
DSW
Data switch chip. Part of the 21171 chipset.
EB164
An evaluation board. A hardware/software applications development platform
for the 21164 Alpha microprocessor and 21171 core logic chipset program.
ECC
Error correction code. A 16-bit ECC is passed on the 21164’s data_check lines
for each 128-bit data transfer.
flash ROM
Flash read-only memory. On the EB164, a 1MB, nonvolatile, writable ROM.
Icache
Instruction cache. An 8KB L1 cache reserved for instructions on the 21164
chip.
IPR
Internal processor register.
Glossary–2