User`s guide

B.5 Bcache Read and Write Timing Calculations
B.5.3 Read/Write Spacing Calculations
The 21164 uses the RD_WR_SPC field as the number of CPU cycles to insert
between a private read operation followed by a private write operation. The
number should be large enough to allow the Bcache drivers to turn off before
the 21164 data drivers are turned on, thus avoiding a data bus clash.
To compute this value, the worst case delay of data_ram_oe_h signal needs to
be determined. The value is given by the following equation:
B.6 Memory Initialization
Eight consecutive row address strobe (RAS) cycles are performed to the system
memory bank to ‘‘wake up’’ the DRAMs. This is done by reading the bank eight
times. The caches are disabled at this point so the read data goes directly to
the DRAMs (except for the Scache, which cannot be turned off).
Good data parity is ensured by writing all memory locations. This is done
by rewriting the full contents of memory with the same data. Reading before
writing memory lengthens the time to initialize data parity, however, it
conserves the memory state for debugging purposes.
B.7 Bcache Initialization
The Bcache is initialized by the following steps:
1. Set the BC_CONTROL register in the CPU to ignore parity/ECC reporting.
2. Turn on the Bcache in the 21164 and the CIA.
3. Sweep the Bcache with read operations at cache block increments.
4. Reenable error reporting.
5. Clear error registers.
When the system is powered up, the Bcache contains UNPREDICTABLE data
in the tag RAMs. As the Bcache is swept for initialization, the old blocks
(referred to as dirty victim blocks) are written back to main memory. These
victim write operations will occur based on the tag address (tag), which stores
the upper part of the address location for the dirty blocks of memory.
Because the tags are unpredictable, the victim write operations could occur
to UNPREDICTABLE addresses. Therefore, these write operations could be
attempted to nonexistent memory. Should this happen, the transaction would
complete and an error will be reported. Therefore, reporting of all nonexistent
memory errors in the CIA must be turned off prior to sweeping.
B–8 SROM Initialization