User`s guide

B.5 Bcache Read and Write Timing Calculations
Once the index signals have reached the SRAMs and the write-enable has
been asserted, it must be determined when the write-enable signal can be
deasserted. This is done by computing how much time it takes to perform the
write operation, assuming the data is already present. This is WRsetup + Taw,
where Taw is the amount of time required by the SRAM to write the data.
This quantity is called Taddress:
However, there is more than just Taddress; it must be determined how long it
takes the data to reach the SRAMs, and how long it needs to be stable before
the write-enable can be deasserted (Tdw):
Tclock is equal to one CPU cycle. Because the 21164 does not send the data to
be written until 1 cycle after the write was started, it must be included in the
time before deassertion.
Therefore, Taddress and Tdata both determine the earliest from the beginning
of a write cycle that the write pulse can be deasserted. The greater of these
two determine the more critical path upon which the write pulse is determined.
Because WRsetup is the earliest that the write pulse can be asserted, and
Taddress and Tdata determine the earliest that the write pulse can be
deasserted, it follows that WRpulse = Maximum of the following:
Once the CPU has deasserted the write-enable signal, it takes some time for it
to reach the SRAMs (write-enable path delay). Therefore, that time must be
taken into account:
The WRsetup requirement is offset by the write-enable path delay (WRhold)
and the WRhold requirement is offset by the address path delay (WRsetup).
The WRsetup and WRhold delays are each then discounted by the fastest
possible delay through the other path. The minimum parameters estimate the
absolute fastest propagation through the address and write-enable paths.
Therefore:
SROM Initialization B–7